Express-SL/SLE
71
Feature
Options
Description
VOC Error Target
2
The VOC margin search error target value [1..65535]
Generate BDAT PEG Margin Data
Disabled
Generate Port Jitter Data
Enable to generate BDAT PCIe margin tables
PCIe Rx CEM Test Mode
Disabled
Enabled
Enable/Disable PEG Rx CEM Loopback Mode
PCIe Spread Spectrum Clocking
Enabled
Disable
Allows disabling of Spread Spectrum Clocking for compliance
testing
7.3.8
Super IO
Feature
Options
Description
Super IO Chip
Info only
W83627DHG Super IO Configuration
Info only
Serial Port 1 Configuration
Serial
Port
Device
Settings
Change
Settings
Enabled
Disabled
IO=3F8h; IRQ=4
Auto
IO=3F8h; IRQ=4
IO=3F8h; IRQ=3,4,5,6,7,9,10,11,12
IO=2F8h; IRQ=3,4,5,6,7,9,10,11,12
IO=3E8h; IRQ=3,4,5,6,7,9,10,11,12
IO=2E8h; IRQ=3,4,5,6,7,9,10,11,12
Enable/Disable Serial Port (COM).
Fixed configuration of serial port.
Select an optimal setting for Super IO device.
Serial Port 2 Configuration
Serial
Port
Device
Settings
Change
Settings
Device
Mode
Enabled
Disabled
IO=2F8h; IRQ=3
Auto
IO=2F8h; IRQ=3
IO=3F8h; IRQ=3,4,5,6,7,9,10,11,12
IO=2F8h; IRQ=3,4,5,6,7,9,10,11,12
IO=3E8h; IRQ=3,4,5,6,7,9,10,11,12
IO=2E8h; IRQ=3,4,5,6,7,9,10,11,12
Standard Serial Port Mode
IrDA Active pulse 1.6 uS
IrDA Active pulse 3/16 bit time
ASKIR Mode
Enable/Disable Serial Port (COM).
Fixed configuration of serial port.
Select an optimal setting for Super IO device.
