Express-SL/SLE
67
7.3.7
PCI and PCIe
Feature
Options
Description
PCI Common Settings
Info only
PCIE Ports 1-4 Configuration
4x1 Port
1x2 2x1 Port
2x2 Port
1x4 Port
Configures PCI-E Port 1-4 of PCH.
[4X1]: Port 1-4 (x1) and Port 8 (x1)
[1x2 2x1]: Port 1 (x2), Port 2 (disabled), Ports 3 and Port 4 (x1)
[2x2]: Port 1-2 (x2) and Port 3-4 (x2)
[1x4]: Port 1 (x4), Ports 2-4 (disabled)
PCIE Ports 5-8 Configuration
4x1 Port
1x2 2x1 Port
Configures PCI-E Port 5-8 of PCH.
[4X1]:Port 5-8 (x1) and Port 8 (x1)
[1x2 2x1]: Port 5 (x2), Port 6 (disabled), Ports 7 and Port 8 (x1)
PCI Latency Timer
32 PCI Bus Clocks
64 PCI Bus Clocks
96 PCI Bus Clocks
128 PCI Bus Clocks
160 PCI Bus Clocks
192 PCI Bus Clocks
224 PCI Bus Clocks
248 PCI Bus Clocks
Value to be programmed into PCI Latency Timer Register.
PCI-X Latency Timer
32 PCI Bus Clocks
64 PCI Bus Clocks
96 PCI Bus Clocks
128 PCI Bus Clocks
160 PCI Bus Clocks
192 PCI Bus Clocks
224 PCI Bus Clocks
248 PCI Bus Clocks
Value to be programmed into PCI Latency Timer Register.
VGA Palette Snoop
Disabled
Enabled
Allow PCI cards that do not contain their own VGA color palette to
access the video core’s palette
PERR# Generation
Disabled
Enabled
Enables or Disables PCI Device to Generate PERR#.
SERR# Generation
Disabled
Enabled
Enables/Disables PCI Device to Generate SERR#.
PCI Express Configuration
Submenu
PEG Configuration
Submenu
7.3.7.1
PCI and PCIe > PCI Express Configuration
Feature
Options
Description
PCI Express Configuration
Info only
PCI Express Clock Gating
Disabled
Enabled
Enable/Disable PCI Express Clock Gating for each root port.
DMI Link ASPM Control
Disabled
Enabled
Enable/Disable control of Active State Power Management on
both NB side and SB side of the DMI Link.
Port8xh Decode
Disabled
Enabled
Port8xh Decode
Compliance Test Mode
Disabled
Enabled
Compliance Test Mode
PCI Express Gen3 EQ Lanes
Submenu
PCI Express Root Port X
Submenu
