ETX-EV133
User’s Manual
Page 32
CPU to PCI Write Buffer
When this field is Enabled, writes from the CPU to the PCI bus are buffered, to compensate for
the speed differences between the CPU and the PCI bus. When Disabled, the writes are not
buffered and the CPU must wait until the write is complete before starting another write cycle.
Choice: Enabled, Disabled.
PCI Dynamic Bursting
This item allows you to enable/ disable the PCI dynamic bursting function.
Choice: Enabled, Disabled
PCI Master 0 WS Write
When Enabled, writes to the PCI bus are executed with zero wait states.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1.
Choice: Enabled, Disabled
PCI#2 Access #1 Retry
When disabled, PCI#2 will not be disconnected until access finishes (default). When enabled,
PCI#2 will be disconnected if max retries are attempted without success.
Choice: Enabled, Disabled
