ETX-EV133
User’s Manual
Page 30
8.5
Advanced Chipset Features
DRAM Clock
This item allows you to set the DRAM Clock. Options are : Host CLK, HCLK+33M, HCLK-33M or
Auto. Please set the item according to the Host (CPU) Clock and DRAM Clock.
DRAM Timing by SPD
If your DIMM memory have SPD ( Serial Presence Detect ) 8-pin IC on module, you can set this
option to Enabled. System will set your DRAM clock and timing from the SPD IC. If the option set
as Disabled, DRAM clock and timing must be set from items below. (DRAM Clock, SDRAM Cycle
Length and Bank Interleave)
SDRAM Cycle Length
This feature is similar to SDRAM CAS Latency Time. It controls the time delay (in clock cycles -
CLKs) that passes before the SDRAM starts to carry out a read command after receiving it. This
also determines the number of CLKs for the completion of the first part of a burst transfer. Thus,
the lower the cycle length, the faster the transaction. However, some SDRAM cannot handle the
lower cycle length and may become unstable. So, set the SDRAM Cycle Length to 2 for optimal
performance if possible but increase it to 3 if your system becomes unstable.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
↑ ↓ → ←
↑ ↓ → ←
↑ ↓ → ←
↑ ↓ → ←
↑ ↓ → ←
:Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-SAfe Defaults F7:Optimized Defaults
DRAM Clock
[
HCLK-33M
]
DRAM Timing By SPD
[Enabled]
SDRAM Cycle Length
3
Bank Interleave
Disabled
P2C/C2P Concurrency
[Enabled]
Video RAM Cacheable
[Disabled]
Display Feature
[CRT]
Panel Type
640x480
OnChip USB
[Enabled]
USB Keyboard Support
[Enabled]
OnChip Sound
[Enabled]
CPU to PCI Write Buffer
[Enabled]
PCI Dynamic Bursting
[Disabled]
PCI Master 0 WS Write
[Enabled]
PCI Delay Transaction
[Disabled]
PCI#2 Access #1 Retry
[Disabled]
Item Help
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