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cExpress-EL User’s Guide

PICMG COM.0 R3.0

Page 42

Copyright © 2021 ADLINK Technology, Inc.

4.4.1.1

USB Root Segmentation

Name

HSIO name on SOC

Comment

USB 0

HSIO 0

from XHCI controller

USB 1

HSIO 1

from XHCI controller

USB 2

N/A

BOM option support by a USB Hub

USB 3

N/A

BOM option support by a USB Hub

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Summary of Contents for cExpress-EL

Page 1: ...User s Guide cExpress EL Revision Rev 1 1 Date 2021 08 11 Part Number 50M 00026 1010...

Page 2: ...ctrical and Electronic Equipment WEEE directive Environmental protection is a top priority for ADLINK We have enforced measures to ensure that our products manufacturing processes components and raw m...

Page 3: ...s cables when installing mounting or un installing removing equipment To avoid electrical shock and or damage to equipment Keep equipment away from water or liquid sources Keep equipment away from hig...

Page 4: ...enoting special levels of information Note This information adds clarity or specifics to text and illustrations Caution This information indicates the possibility of minor physical injury component da...

Page 5: ...s EL User s Guide PICMG COM 0 R3 0 Page 4 Copyright 2021 ADLINK Technology Inc Revision History Revision Description Date Author 1 0 Initial release 2021 06 03 1 1 Update specs mechanical drawings 202...

Page 6: ...t 12 2 6 Multi I O and Storage 12 2 7 Trusted Platform Module TPM 14 2 8 SEMA Board controller 14 2 9 Debug 14 2 10 Power 14 2 11 Mechanical and Environmental 15 3 Block Diagram 16 4 Pinout and Signal...

Page 7: ...DDI3 Port 50 4 4 6 PCIe Graphics Port PEG 50 4 4 7 Module Type Definition 51 4 4 8 Power and Ground 52 5 Additional Features 53 5 1 Debug Connector 54 5 2 Status LEDs 55 5 3 Fan Connector 57 5 4 BIOS...

Page 8: ...ock Diagram 16 Figure 2 Module Rear Side Row and Pin Numbering 17 Figure 3 Module feature locations 53 Figure 4 COM Express Compact Size Module and Debug Module 54 Figure 5 Module Dimensions 64 Figure...

Page 9: ...and OT in a simplified design The cExpress EL supports BIOS configurable in band ECC IBECC with up to two SODIMM sockets and a maximum 32GB DDR4 3200 MT s memory capacity to support mission critical...

Page 10: ...CC non ECC Intel TCC Intel Atom x6200FE 1 0 GHz 4 5W 2C No GPU IBECC non ECC Intel TCC Intel Pentium J6426 2 0 3 0 GHz 10W 4C 32EU non ECC Intel Celeron J6413 1 8 3 0 GHz 10W 4C 16EU non ECC Intel Pen...

Page 11: ...5MB Embedded BIOS AMI Aptio V UEFI with CMOS backup in 16 or 32 MB SPI BIOS 2 2 Video GPU Intel Gen 11 LP Graphics core architecture GPU Feature Support 3 independent and simultaneous combinations of...

Page 12: ...1 Display Interface Support LVDS Single dual channel 18 24 bit LVDS through eDP to LVDS supports DE mode and Hsync Vsync mode Max resolution is 1920x1200 60Hz in dual mode Pixel clock frequency up to...

Page 13: ...ports 2 5Gbit s or 1000 100 10 Mbit s connection Supports TSN on Yocto Linux dependent on GPY215 and CPU SKU with Intel TCC feature TSN supported by project basis 2 6 Multi I O and Storage USB Up to 4...

Page 14: ...0x248 Yes SER0 SER1 from SoC HSUART is a BOM option supported by project basis LPC Bus Low Pin Count bus extends from an eSPI to LPC bridge IC GPIO or SD 4 GPO and 4 GPI GPI with interrupt SD GPIO mu...

Page 15: ...0 pin flat cable connector to be used with DB 30 x86 debug module Supports BIOS POST code LED BMC access SPI BIOS flashing internal power rail test points debug LEDs 2 10 Power Power Modes AT and ATX...

Page 16: ...de Voltage Input Storage 20 C to 80 C Extreme Rugged 40 C to 85 C Standard Voltage Input Storage 40 C to 85 C selected processor SKUs Humidity 5 90 RH operating non condensing 5 95 RH storage and oper...

Page 17: ...tom side 3200 MT s non ECC IBECC DDR4 SODIMM top side 3200 MT s non ECC IBECC LAN PHY MaxLinear GPY Series VGA eDP LVDS USB 2 0 Lane 0 7 SATA Port 0 1 Max 2 5GbE PCIe Lane 0 3 PCIe Lane 4 5 HDA SPI SM...

Page 18: ...e is a comprehensive list of all signal pins supported on the dual 220 pin COM Express connectors as defined for Type 6 in the PICMG COM 0 Rev 3 0 specification Signals described in the specification...

Page 19: ...R6 D15 DDI1_CTRLCLK_AUX A16 SATA0_TX B16 SATA1_TX C16 DDI1_PAIR6 D16 DDI1_CTRLDATA_AUX A17 SATA0_TX B17 SATA1_TX C17 RSVD D17 RSVD A18 SUS_S4 B18 SUS_STAT ESPI_RESET C18 RSVD D18 RSVD A19 SATA0_RX B19...

Page 20: ...LPC_SERIRQ ESPI_CS1 B50 CB_RESET C50 DDI3_PAIR3 D50 DDI2_PAIR3 A51 GND FIXED B51 GND FIXED C51 GND FIXED D51 GND FIXED A52 PCIE_TX5 B52 PCIE_RX5 C52 PEG_RX0 D52 PEG_TX0 A53 PCIE_TX5 B53 PCIE_RX5 C53 P...

Page 21: ...AT eDP_AUX B84 VCC_5V_SBY C84 GND D84 GND A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10 D85 PEG_TX10 A86 RSVD B86 VCC_5V_SBY C86 PEG_RX10 D86 PEG_TX10 A87 eDP_HPD B87 VCC_5V_SBY C87 GND D87 GND A88 PCIE0_CK_RE...

Page 22: ...B108 VCC_12V C108 VCC_12V D108 VCC_12V A109 VCC_12V B109 VCC_12V C109 VCC_12V D109 VCC_12V A110 GND FIXED B110 GND FIXED C110 GND FIXED D110 GND FIXED Notes STRIKETHROUGH strikethrough entries are not...

Page 23: ...3 3V tolerant I O 5V Bi directional signal 5V tolerant I O 3 3VSB Input or output 3 3V tolerant active in standby state DDC Display Data Channel PCIE PCI Express compatible differential signal PEG PC...

Page 24: ...CODEC active low O 3 3VSB AC_SYNC HDA_SYNC A29 Sample synchronization signal to the CODEC s O 3 3V AC_BITCLK HDA_BITCLK A32 Serial data clock generated by the external CODEC s I O 3 3V AC_SDOUT HDA_SD...

Page 25: ...drive a 37 5 Ohm equivalent load O Analog PD 150R VGA_BLU B92 Blue for monitor Analog DAC output designed to drive a 37 5 Ohm equivalent load O Analog PD 150R VGA_HSYNC B93 Horizontal sync output to...

Page 26: ...below Pin LVDS mode eDP mode A71 A72 LVDS_A0 LVDS_A0 eDP_TX2 eDP_TX2 A73 A74 LVDS_A1 LVDS_A1 eDP_TX1 eDP_TX1 A75 A76 LVDS_A2 LVDS_A2 eDP_TX0 eDP_TX0 A78 A79 LVDS_A3 LVDS_A3 A81 A82 LVDS_A_CK LVDS_A_CK...

Page 27: ...LVDS_B0 LVDS_B0 LVDS_B1 LVDS_B1 LVDS_B2 LVDS_B2 LVDS_B3 LVDS_B3 B71 B72 B73 B74 B75 B76 B77 B78 LVDS Channel B differential pairs O LVDS LVDS_B_CK LVDS_B_CK B81 B82 LVDS Channel B differential clock...

Page 28: ...ifferential pairs O PCIE AC coupled off module eDP_VDD_EN A77 eDP power enable O 3 3V PD 100K eDP_BKLT_EN B79 eDP backlight enable O 3 3V PD 100K eDP_BKLT_CTRL B83 eDP backlight brightness control O 3...

Page 29: ...Controller 0 link indicator active low OD 3 3VSB LED behaviour is TBC GBE0_LINK100 A4 Gigabit Ethernet Controller 0 100Mbit sec link indicator active low OD 3 3VSB LED behaviour is TBC GBE0_LINK1000 A...

Page 30: ...ve Input differential pair I SATA AC coupled on Module SATA2_TX SATA2_TX A22 A23 Serial ATA channel 2 Transmit Output differential pair O SATA Not supported SATA2_RX SATA2_RX A25 A26 Serial ATA channe...

Page 31: ..._RX2 PCIE_RX2 B61 B62 PCI Express channel 2 Receive Input differential pair I PCIE AC coupled off Module PCIE_TX3 PCIE_TX3 A58 A59 PCI Express channel 3 Transmit Output differential pair O PCIE AC cou...

Page 32: ...3 0 Page 31 Copyright 2021 ADLINK Technology Inc 4 3 6 1 PCH HSIO Lane Assignments Name HSIO name on SOC Comment PCIE0 HSIO 2 PCIE1 HSIO 3 PCIE2 HSIO 4 PCIE3 HSIO 5 PCIE4 HSIO 8 PCIE5 HSIO 6 PCIE6 N A...

Page 33: ...ed address command and data bus I O 3 3V LPC_FRAME B3 LPC frame indicates the start of an LPC cycle O 3 3V LPC_DRQ0 LPC_DRQ1 B8 B9 LPC serial DMA request I 3 3V Not connected LPC_SERIRQ A50 LPC serial...

Page 34: ...B_0_1_OC B44 USB over current sense USB ports 0 and 1 A pull up for this line shall be present on the module An open drain driver from a USB current monitor on the carrier board may drive this line lo...

Page 35: ...A94 Clock from module to carrier board SPI BIOS flash O 3 3VSB SPI_POWER A91 Power supply for Carrier Board SPI sourced from Module nominally 3 3V The Module shall provide a minimum of 100mA on SPI_PO...

Page 36: ...RMTRIP A35 Active low output indicating that the CPU has entered thermal shutdown O 3 3V PU 10K 3 3V FAN_PWMOUT B101 Fan speed control Uses the Pulse Width Modulation PWM technique to control the fan...

Page 37: ...Management Bus Alert active low input can be used to generate an SMI System Management Interrupt or to wake the system Power sourced through 3 3V standby rail and main power rails I 3 3VSB Note SMBus...

Page 38: ...3V After hardware RESET output low GPO 3 B63 General purpose output pins O 3 3V PD 10K 3 3V After hardware RESET output low GPI 0 A54 General purpose input pins Pulled high internally on the module I...

Page 39: ...ll be PD on carrier board SER0_RX A99 General purpose serial port receiver I CMOS 3 3V PU 10K 3 3V Power rail tolerance 5V 12V SER1_TX CAN A101 General purpose serial port transmitter O CMOS 3 3V Powe...

Page 40: ...peration used to notify LPC devices O 3 3VSB SUS_S3 A15 Indicates system is in Suspend to RAM state Active low output An inverted copy of SUS_S3 on the carrier board also known as PS_ON may be used to...

Page 41: ...used P 8 5 20 V VCC_5V_SBY B84 B85 B86 B87 Standby power input 5 0V nominal If VCC5_SBY is used all available VCC_5V_SBY pins on the connector s shall be used Only used for standby and suspend functi...

Page 42: ...le USB_SSTX1 USB_SSTX1 D6 D7 Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB1 O PCIE AC coupled on module USB_SSRX2 USB_SSRX2 C9 C10 Additional Receive signal dif...

Page 43: ...Copyright 2021 ADLINK Technology Inc 4 4 1 1 USB Root Segmentation Name HSIO name on SOC Comment USB 0 HSIO 0 from XHCI controller USB 1 HSIO 1 from XHCI controller USB 2 N A BOM option support by a...

Page 44: ...press channel 6 Transmit Output differential pair O PCIE Not supported PCIE_RX6 PCIE_RX6 C19 C20 PCI Express channel 6 Receive Input differential pair I PCIE Not supported PCIE_TX7 PCIE_TX7 D22 D23 PC...

Page 45: ...DDI1_PAIR5 C29 C30 DDI1_PAIR6 DDI1_PAIR6 C15 C16 DDI1_HPD C24 DP1_HPD HDMI1_HPD DDI1_CTRLCLK_AUX D15 DP1_AUX HMDI1_CTRLCLK DDI1_CTRLCLK_AUX D16 DP1_AUX HMDI1_CTRLDATA DDI1_DDC_AUX_SEL D34 DDI1_DDC_AUX...

Page 46: ...g Unplug and notification of the link layer I 3 3V PD 100K Module must tolerate high level in stand by mode The carrier board shall include a blocking FET on DP1_HPD to prevent back drive current from...

Page 47: ...itors shall be placed on the Carrier TMDS1_CLK TMDS1_CLK D36 D37 HDMI Port Differential Pair Clock Lines HDMI_HPD C24 Detection of Hot Plug Unplug and notification of the link layer I 3 3V PD 100K HDM...

Page 48: ...TMDS2_CLK DDI2_HPD D44 DP2_HPD HDMI2_HPD DDI2_CTRLCLK_AUX C32 DP2_AUX HMDI2_CTRLCLK DDI2_CTRLCLK_AUX C33 DP2_AUX HMDI2_CTRLDATA DDI2_DDC_AUX_SEL C34 DDI2_DDC_AUX_SEL DDI2_DDC_AUX_SEL Note Dual Mode HD...

Page 49: ...g Unplug and notification of the link layer I 3 3V PD 100K Module must tolerate high level in stand by mode The carrier board shall include a blocking FET on DP1_HPD to prevent back drive current from...

Page 50: ...itors shall be placed on the Carrier TMDS2_CLK TMDS2_CLK D49 D50 HDMI Port Differential Pair Clock Lines HDM2_HPD D44 Detection of Hot Plug Unplug and notification of the link layer I 3 3V PD 100K HDM...

Page 51: ...cExpress EL User s Guide PICMG COM 0 R3 0 Page 50 Copyright 2021 ADLINK Technology Inc 4 4 5 DDI3 Port Not supported on this module 4 4 6 PCIe Graphics Port PEG Not supported on this module...

Page 52: ...t present X TYPE2 TYPE1 TYPE0 X X X Pinout Type 1 X X X Pinout Type 10 NC NC NC Pinout Type 2 NC NC GND Pinout Type 3 NC GND NC Pinout Type 4 NC GND GND Pinout Type 5 GND NC NC Pinout Type 6 GND NC GN...

Page 53: ...D105 D106 D107 D108 D109 Primary power input supports wide range 5 20V input All available VCC_12V pins on the connector s shall be used P 8 5 20 V GND C1 C2 C5 C8 C11 C14 C21 C31 C41 C51 C60 C70 C73...

Page 54: ...is chapter describes the connectors LEDs and switches located on the module and are not necessarily included in the PICMG standard specification The locations of these parts are as shown below Figure...

Page 55: ...r useful during carrier design and bring up phase It offers access to the following critical parts of the module Test points for measurement of internal power rails SPI BIOS programming interface I2C...

Page 56: ...des Table below LED2 Green Power Source 3Vcc S0 LED ON S3 S4 S5 LED OFF ECO mode LED OFF LED3 Red BMC output and same signal as WDT B27 on BtB connector Module power up WD LED LED OFF Watchdog countin...

Page 57: ...OERROR 2 NO_SUSCLK 3 NO_SLP_S5 4 NO_SLP_S4 5 NO_SLP_S3 6 BIOS_FAIL 7 RESET_FAIL 8 RESETIN_FAIL 9 NO_CB_PWROK 10 CRITICAL_TEMP 11 POWER_FAIL 12 VOLTAGE_FAIL 13 RSMRST_FAIL 14 NO_VDDQ_PG 15 NO_V1P05A_PG...

Page 58: ...dule s input voltage VCC_12V pins If the module s input voltage is 12V or lower the supply voltage will be equal to the module s input voltage and the maximum supply current of the fan connector will...

Page 59: ...default BIOS settings follow the steps below 1 Shut down the system 2 Hold down the BIOS Setup Defaults Reset Button continuously and boot up the system You can release the button when the BIOS promp...

Page 60: ...ed in the SPI0 slot on the carrier In dual BIOS Failsafe mode both BIOS chips on the module are configured as SPI1 Only one of the two is connected to the SPI bus at any given time In case of failure...

Page 61: ...e very useful in aiding software developers or technicians in debugging problems that occur during the pre boot process on production hardware Beep code is a series of short sound signals Beep codes a...

Page 62: ...play Checkpoint cards are available through a variety of computer mail order outlets Newer systems feature support for AMI Debug Rx a USB connected alternative to the PCI POST Card AMI Debug Rx is a l...

Page 63: ...SEC errors 0x10 0x2F PEI execution up to and including memory detection 0x30 0x4F PEI execution after memory detection 0x50 0x5F PEI errors 0x60 0x8F DXE execution up to BDS 0x90 0xCF BDS execution 0...

Page 64: ...ge 63 Copyright 2021 ADLINK Technology Inc 7 Software Support 7 1 1 Windows 10 IOT Enterprise 64 bit 7 1 2 Yocto Linux 64 bit https github com ADLINK meta adlink x86 64bit 7 1 3 Ubuntu Under planning...

Page 65: ...bottom side 5 2 4 2 Right View 0 4 16 5 18 99 74 2 80 95 4 91 12 67 87 67 0 4 6 18 34 99 53 7 91 56 9 4 91 95 74 99 Bottom View Bottom Side SODIMM Keep out Zone Top View Side View Figure 5 Module Dim...

Page 66: ...press EL User s Guide PICMG COM 0 R3 0 Page 65 Copyright 2021 ADLINK Technology Inc 8 2 Thermal Solutions 8 2 1 Heatspreader HTS 11 8 95 95 65 87 87 76 M2 5 2pcs M2 5 4pcs Figure 6 Heatspreader HTS cE...

Page 67: ...cExpress EL User s Guide PICMG COM 0 R3 0 Page 66 Copyright 2021 ADLINK Technology Inc 8 2 2 Heatsink THS 16 8 95 95 87 87 M2 5 2pcs M2 5 4pcs Figure 7 Heatsink THS cEL B I...

Page 68: ...cExpress EL User s Guide PICMG COM 0 R3 0 Page 67 Copyright 2021 ADLINK Technology Inc 8 2 3 Heatsink THSH 30 7 8 95 95 76 87 M2 5 2pcs M2 5 4pcs Figure 8 Heatsink THSH cEL B I...

Page 69: ...cExpress EL User s Guide PICMG COM 0 R3 0 Page 68 Copyright 2021 ADLINK Technology Inc 8 2 4 Active Cooling THSF 87 87 95 95 42 55 8 M2 5 4pcs M2 5 2pcs Figure 9 Heatsink THSH cEL B I...

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