cExpress-EL User’s Guide
PICMG COM.0 R3.0
Page 12
Copyright © 2021 ADLINK Technology, Inc.
2.4
Expansion Busses
6 PCI Express x1 Gen3: Lanes 0,1,2,3,4,5
PCIe lanes 0-4 can be configured to x1, x2, x4 (for example, 1 x4 or 2 x2 or 1 x2 + 2 x1)
PCIe lanes 4,5 can only be x1 configuration
Other: SMBus (system), I2C (user)
2.5
Ethernet
Integrated MAC with MaxLinear® 2.5Gigabit Ethernet PHY, GPY211 or GPY215
Supports 2.5Gbit/s or 1000/100/10 Mbit/s connection
Supports TSN on Yocto Linux (dependent on GPY215 and CPU SKU with Intel® TCC feature, TSN supported by project basis)
2.6
Multi I/O and Storage
USB
Up to 4x USB 3.2 Gen1 (USB 0,1,2,3; via USB hub, project basis), 4x USB 2.0 (USB 4,5,6,7)
Default support is 2x USB 3.2 Gen2 (USB 0,1), 6x USB 2.0 (USB 2,3,4,5,6,7)
SuperSpeedPlus, SuperSpeed, High-Speed, Full-Speed and Low-Speed USB signalling
Note: Carrier board must be designed for Gen2 operation.
UART/CAN
Two UART interfaces SER0 and SER1 RX/TX on Module
Console Redirection COM 1 or COM 2 selectable in BIOS
