cExpress-EL User’s Guide
PICMG COM.0 R3.0
Page 16
Copyright © 2021 ADLINK Technology, Inc.
3.
Block Diagram
C
AB
DDI 3
DDI 2
DDI 1
USB 3.2 Lane 0
USB 3.2 Lane 1
USB 3.2 Lane 2
USB 3.2 Lane 3
PCIe Lane 6
PCIe Lane 7
PEG Port
PEG 0-15
6th Generation
Intel Atom® x6000E
(formerly “Elkhart Lake”)
DP to VGA
eDP to LVDS
eDP
build option
build option, eDP 4lanes
SATA 6Gbps
(HSIO 10-11)
DDR4 SODIMM
(bottom side)
3200 MT/s, non-ECC/IBECC
DDR4 SODIMM
(top side)
3200 MT/s, non-ECC/IBECC
LAN PHY
(MaxLinear GPY Series)
VGA
eDP/LVDS
USB 2.0 Lane 0-7
SATA Port 0-1
Max. 2.5GbE
PCIe Lane 0-3
PCIe Lane 4-5
HDA
SPI
SMBus
I
2
C
GPIO/SDIO
UART 0-1
LPC
(HSIO 0)
USB 3.2 Gen2 x1
USB 3 Hub
build option
4 PCIe Gen3
(HSIO 2-5)
2 PCIe Gen3
(HSIO 8, 6)
x4, x2, x1 config.
2 x1 config. only
eSPI
TPM 2.0
build option
build option
eSPI to LPC
I
2
C
SDIO 3.0
HSUART
Thermal
sensor
(SoC)
Thermal
sensor
(board)
MUX
Embedded Controller
SMBus
BIOS
BIOS
eMMC 5.1
16GB-64GB
(HSIO 1)
USB 3.2 Gen2 x1
Figure 1 – Module Function Block Diagram
