ADLINK Technology cExpress-AL User Manual Download

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cExpress-AL

BIOS Setup

Feature

Options

Description

NFER

Disable

Enable

PCI Express Device Non-Fatal Error Reporting
Enable/Disable

CER

Disable

Enable

PCI Express Device Correctable Error Reporting
Enable/Disable

CTO

Default Setting

16-15 ms
65-210 ms
260-900 ms
1-3.5 s
Disable

PCI Express Completion Timer TO Enable/Disable.

SEFE

Disable

Enable

Root PCI Express System Error on Fatal Error
Enable/Disable

SENFE

Disable

Enable

Root PCI Express System Error on Non-Fatal Error
Enable/Disable

SECE

Disable

Enable

Root PCI Express System Error on Correctable Error
Enable/Disable

PME SCI

Disable

Enable

PCI Express PME SCI Enable/Disable

Hot Plug

Disable

Enable

PCI Express Hot Plug Enable/Disable

PCIe Speed

Auto

Gen1
Gen2

Configure PCIe Speed

Transmitter Half Swing

Disable

Enable

Transmitter Half Swing Enable/Disable.

Extra Bus Reserved

Extra Bus Reserved (0-7) for bridges behind this Root
Bridge

Reserved Memory

Reserved Memory and Prefetchable Memory (1-
20MB) Range for this Root Bridge

Reserved I/O

Reserved I/O (4K/8K/12K/16K/20K) Range for this
Root Bridge

PCH PCIe LTR Configuration

Info only

PCH PCIE LTR

Disable

Enable

PCH PCIE Latency Reporting Enable/Disable

Snoop Latency Override

Disabled
Manual

Auto

Snoop Latency Override for PCH PCIE.
Disabled: Disable override.
Manual: Manually enter override values.
Auto (default): Maintain default BIOS flow.

Non Snoop Latency Override

Disabled
Manual

Auto

Non Snoop Latency Override for PCH PCIE.
Disabled: Disable override.
Manual: Manually enter override values.
Auto (default): Maintain default BIOS flow

PCIE LTR Lock

Disable

Enable

PCIE LTR Configuration Lock

PCIe Selection De0emphasis

Disable

Enable

When the Link is operating at 5.0 GT/s speed, this bit
selects the level of de-emphasis for an Upstream
component.
1b -3.5 dB
0b -6 dB

Summary of Contents for cExpress-AL

Page 1: ...Leading EDGE COMPUTING cExpress AL User s Manual COM Express Compact Size Type 6 Module with Intel Atom Pentium Celeron SoC Manual Rev 1 0 Revision Date December 4 2017 Part Number 50 1J068 1000 ...

Page 2: ... such damages Environmental Responsibility ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union s Restriction of Hazardous Substances RoHS directive and Waste Electrical and Electronic Equipment WEEE directive Environmental protection is a top priority for ADLINK We have enforced measures to ensure that our product...

Page 3: ...ifications 6 2 12 Operating Temperatures 6 2 13 Environmental 6 2 14 Specification Compliance 6 2 15 Operating Systems 6 2 16 Functional Diagram 7 2 17 Mechanical Drawing 8 3 Pinouts and Signal Descriptions 9 3 1 AB CD Pin Definitions 9 3 2 Signal Description Terminology 12 3 3 AB Signal Descriptions 13 3 4 CD Signal Descriptions 23 4 Module Interfaces 31 4 1 Connector Switch and LED Locations 31 ...

Page 4: ...ap 49 6 6 SMBus Address Table 50 7 BIOS Setup 51 7 1 Menu Structure 51 7 2 Main 52 7 3 Advanced 54 7 4 Chipset 69 7 5 Security Menu 80 7 6 Boot Menu 80 7 7 Save Exit Menu 81 8 BIOS Checkpoints Beep Codes 83 8 1 Status Code Ranges 84 8 2 Standard Status Codes 84 8 3 OEM Reserved Checkpoint Ranges 91 9 Mechanical Information 93 9 1 Board to Board Connectors 93 9 2 Thermal Solution 94 9 3 Mounting Me...

Page 5: ...agram 7 Figure 2 cExpress AL Mechanical Drawing 8 Figure 3 cExpress AL Connector Switch and LED Locations 31 Figure 4 cExpress AL and the DB40 Debug Module 31 Figure 5 cExpress AL Switch Locations 37 Figure 6 COM Express Mounting Methods 97 Figure 7 COM Express Standoff Types 98 ...

Page 6: ... 32 Table 3 cExpress AL LED Descriptions 33 Table 4 MIPI60 Debug Header Pin Definition 34 Table 5 Fan Connector Pin Definition 35 Table 6 BIOS Select and Mode Configuration Switch Settings 37 Table 7 SEMA Onboard Voltage Monitor 40 Table 8 SEMA BMC Status 40 Table 9 SEMA Exception Codes 41 Table 10 SEMA BMC Flags 41 ...

Page 7: ...P9 MVC JPEG MJPEG hardware decode Up to three independent displays are available from DDI ports supporting HDMI DVI DisplayPort optional VGA single dual channel 18 24 bit LVDS and optional eDP The cExpress AL is specifically designed for customers with balanced performance power consumption requirements who want to outsource the custom core logic of their systems for reduced development time The c...

Page 8: ...2 Introduction This page intentionally left blank ...

Page 9: ...SE4 2 Intel 64 architecture Intel Turbo Boost Technology 2 0 Intel AES NI Intel TXT PCLMULQDQ instruction DRNG Notes Availability of features may vary between processor SKUs and operating systems Only Atom SKUs can support extreme temperature operating range Cache 2MB for all SKUs Memory Dual channel non ECC 1600 1867 MHz DDR3L memory up to 8GB in dual stacked SODIMM sockets lower slot must be pop...

Page 10: ...b DVI VGA via DP to VGA IC by build option in place of DDI2 Note Only two simultaneous HDMI DVI outputs supported 2 4 Audio Integrated Intel HD Audio integrated on SoC Codec Located on carrier Express BASE6 ALC886 standard support 2 5 LAN MAC PHY Intel i210 Ethernet controller Intel i211 is supported by project basis Interface 10 100 1000 Mbit s connection IEEE 1588 support Notes PCIe port 5 is su...

Page 11: ...Yes COM 2 Supported by module SER1 A101 A102 via NCT5104D 11 0x248 Yes COM 3 Supported by Super I O W83627DHG on carrier board 4 0x3F8 Yes COM 4 Supported by Super I O W83627DHG on carrier board 3 0x2F8 Yes 2 8 SEMA Board Controller z Type ADLINK Smart Embedded Management Agent SEMA z Functions Voltage Current monitoring Power sequence debug support AT ATX mode control Logistics and forensic infor...

Page 12: ... C to 60 C Wide Voltage Input Storage 20 C to 70 C Extreme Rugged Operating Temperature optional 40 C to 85 C Standard Voltage Input only build option supported by Atom SKUs only Storage 40 C to 85 C 2 13 Environmental Humidity Operating 5 90 RH non condensing Storage 5 95 RH and operating with conformal coating Shock and Vibration IEC 60068 2 64 and IEC 60068 2 27 MIL STD 202F Method 213B Table 2...

Page 13: ... 2 Single dual channel 18 24 bit LVDS eDP LM73 SEMA BMC SMBus GP I2C SPI 0 BIOS LPC bus SPI SPI 1 BIOS DDC I2C SPI_CS SODIMM 1867 1600 MHz 2 8 GB DDR3L non ECC eDP x4 lanes build option LVDS eDP to LVDS 4x GPI 4x GPO SD GPIO SD PCIe x1 port0 PCIe x1 port1 PCIe x1 port2 PCIe Bridge build option PCIe x1 port3 PCIe x1 port4 GbE TPM 2 0 build option I2C MUX VGA DP to VGA build option Note max capacity...

Page 14: ... 4 91 42 95 95 95 88 34 74 54 82 93 connector on bottom side 3 25 2 5 2 9 2 All are dimensions shown in millimeters Tolerances should be 0 25mm unless otherwise noted The tolerances of the module connector locating peg holes 16 50 6 00 and 16 50 18 00 should be 0 10mm Figure 2 cExpress AL Mechanical Drawing ...

Page 15: ...WRBTN C12 USB_SSRX3 D12 USB_SSTX3 A13 GBE0_MDI0 B13 SMB_CK C13 USB_SSRX3 D13 USB_SSTX3 A14 GBE0_CTREF B14 SMB_DAT C14 GND D14 GND A15 SUS_S3 B15 SMB_ALERT C15 DDI1_PAIR6 D15 DDI1_CTRLCLK_AUX A16 SATA0_TX B16 SATA1_TX C16 DDI1_PAIR6 D16 DDI1_CTRLDATA_AUX A17 SATA0_TX B17 SATA1_TX C17 RSVD D17 RSVD A18 SUS_S4 B18 SUS_STAT C18 RSVD D18 RSVD A19 SATA0_RX B19 SATA1_RX C19 PCIE_RX6 D19 PCIE_TX6 A20 SATA...

Page 16: ...4 GPI0 B54 GPO1 C54 TYPE0 D54 PEG_LANE_RV A55 PCIE_TX4 B55 PCIE_RX4 C55 PEG_RX1 D55 PEG_TX1 A56 PCIE_TX4 B56 PCIE_RX4 C56 PEG_RX1 D56 PEG_TX1 A57 GND B57 GPO2 C57 TYPE1 D57 TYPE2 A58 PCIE_TX3 B58 PCIE_RX3 C58 PEG_RX2 D58 PEG_TX2 A59 PCIE_TX3 B59 PCIE_RX3 C59 PEG_RX2 D59 PEG_TX2 A60 GND fixed B60 GND fixed C60 GND fixed D60 GND fixed A61 PCIE_TX2 B61 PCIE_RX2 C61 PEG_RX3 D61 PEG_TX3 A62 PCIE_TX2 B6...

Page 17: ..._PP B96 VGA_I2C_DAT C96 GND D96 GND A97 TYPE10 B97 SPI_CS C97 RSVD D97 RSVD A98 SER0_TX B98 RSVD C98 PEG_RX14 D98 PEG_TX14 A99 SER0_RX B99 RSVD C99 PEG_RX14 D99 PEG_TX14 A100 GND fixed B100 GND fixed C100 GND fixed D100 GND fixed A101 SER1_TX B101 FAN_PWMOUT C101 PEG_RX15 D101 PEG_TX15 A102 SER1_RX B102 FAN_TACHIN C102 PEG_RX15 D102 PEG_TX15 A103 LID B103 SLEEP C103 GND D103 GND A104 VCC_12V B104 ...

Page 18: ... O 5V Output 5V signal level I O 3 3V Bi directional signal 3 3V tolerant I O 5V Bi directional signal 5V tolerant I O 3 3Vsb Input 3 3V tolerant active in standby state P Power Input Output REF Reference voltage output that may be sourced from a module power plane PDS Pull down strap This is an output pin on the module that is either tied to GND or not connected The signal is used to indicate the...

Page 19: ...uidance 3 3 2 Analog VGA build option Signal Pin Description I O PU PD Comment VGA_RED B89 Red for monitor Analog DAC output designed to drive a 37 5 Ohm equivalent load O Analog PD 150R VGA_GRN B91 Green for monitor Analog DAC output designed to drive a 37 5 Ohm equivalent load O Analog PD 150R VGA_BLU B92 Blue for monitor Analog DAC output designed to drive a 37 5 Ohm equivalent load O Analog PD...

Page 20: ...le O 3 3V LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3 3V PD 100k ePD to LVDS requirement LVDS_I2C_CK A83 DDC lines used for flat panel detection and control O 3 3V PU 2k2 3 3V LVDS_I2C_DAT A84 DDC lines used for flat panel detection and control I O 3 3V PU 2k2 3 3V eDP build option Signal Pin Description I O PU PD Comment eDP_TX2 eDP_TX2 eDP_TX1 eDP_TX1 eDP_TX0 eDP_TX0 A71 A72 A...

Page 21: ...s 3 3V The reference voltage output shall be current limited on the Module In the case in which the reference is shorted to ground the current shall be 250 mA or less GND min 3 3V max Not supported NC pin GBE0_SDP A49 Gigabit Ethernet Controller 0 Software Definable Pin Can also be used for IEEE1588 support such as a 1pps signal 3 3 5 SATA Signal Pin Description I O PU PD Comment SATA0_TX SATA0_TX...

Page 22: ...ss channel 4 Transmit Output differential pair O PCIE AC coupled on module PCIe port 4 is by build option by PCIe bridge IC PCIE_RX4 PCIE_RX4 B55 B56 PCI Express channel 4 Receive Input differential pair I PCIE AC coupled off module PCIe port 4 is by build option by PCIe bridge IC PCIE_TX5 PCIE_TX5 A52 A53 PCI Express channel 5 Transmit Output differential pair O PCIE AC coupled on module PCIe por...

Page 23: ...e present on the module An open drain driver from a USB current monitor on the carrier board may drive this line low I 3 3VSB PU 10k 3 3VSB Do not pull high on carrier USB_2_3_OC A44 USB over current sense USB ports 2 and 3 A pull up for this line shall be present on the module An open drain driver from a USB current monitor on the carrier board may drive this line low I 3 3VSB PU 10k 3 3VSB Do no...

Page 24: ... 2 0 USB 3 0 USB 2 0 USB 3 0 USB 2 0 USB 3 0 USB 2 0 USB 3 0 USB 2 0 USB 3 0 xHCI Engine SoC USB 2 0 Port 0 Host Device USB 2 0 Port 7 USB 2 0 Port 1 USB 2 0 Port 2 USB 2 0 Port 3 USB 2 0 Port 4 USB 2 0 Port 5 USB 2 0 Port 6 USB 3 0 Upgrade Port 0 USB 3 0 Upgrade Port 1 USB 3 0 Upgrade Port 2 USB 3 0 Upgrade Port 3 ROW CD ROW AB USB 2 0 Port 5 USB 2 0 Port 4 USB 2 0 Port 3 USB 2 0 Port 2 USB 3 0 2...

Page 25: ...U 10k 3 3VSB Carrier shall pull to GND or leave not connected 3 3 11 Miscellaneous Signal Pin Description I O PU PD Comment SPKR B32 Output for audio enunciator the speaker in PC AT systems O 3 3V PU 10k 3 3V WDT B27 Output indicating that a watchdog time out event has occurred O 3 3V THRM B35 Input from off module temp sensor indicating an over temp situation I 3 3V Recommend to add PU on carrier...

Page 26: ...A BMC or Braswell SoC as alternative BMC by default 3 3 14 General Purpose I O GPIO Signal Pin Description I O PU PD Comment GPO 0 A93 General purpose output pins O 3 3V PD 10k After hardware RESET output low GPO 1 B54 General purpose output pins O 3 3V PD 10k After hardware RESET output low GPO 2 B57 General purpose output pins O 3 3V PD 10k After hardware RESET output low GPO 3 B63 General purpo...

Page 27: ...e PD on carrier board SER1_RX A102 General purpose serial port receiver TTL level input I CMOS PU 4 7k 5V Power rail tolerance 5V 12V 3 3 16 Power And System Management Signal Pin Description I O PU PD Comment PWRBTN B12 Power button to bring system out of S5 soft off active on falling edge I 3 3VSB PU 10k 3 3VSB SYS_RESET B49 Reset button input Active low request for module to reset and reboot Ma...

Page 28: ...B LID A103 LID button Low active signal used by the ACPI operating system for a LID switch I OD 3 3VSB PU 10k 3 3VSB Emulated on GPIO BIOS SLEEP B103 Sleep button Low active signal used by the ACPI operating system to bring the system to sleep state or to wake it up again I OD 3 3VSB PU 10k 3 3VSB Emulated on GPIO BIOS Note PU 47K 3 3VSB supported by project basis Please contact your local represe...

Page 29: ...ntial pairs for the SuperSpeed USB data path on USB2 I PCIE AC coupled off Module USB_SSTX2 USB_SSTX2 D9 D10 Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB2 O PCIE AC coupled on Module USB_SSRX3 USB_SSRX3 C12 C13 Additional Receive signal differential pairs for the SuperSpeed USB data path on USB3 I PCIE Not supported USB_SSTX3 USB_SSTX3 D12 D13 Additional Tr...

Page 30: ...E PD 100K IF DDI1_DDC_AUX_SEL is floating I O PCIe PD 100K DP1_AUX AC coupled on Module DDI1_CTRLCLK_AUX D15 IF DDI1_DDC_AUX_SEL pulled high I O OD 3 3V HDMI1_CTRLCLK PU 10k 3 3V IF DDI1_DDC_AUX_SEL is floating I O PCIe PU 100K 3 3V DP1_AUX AC coupled on Module DDI1_CTRLDATA_AUX D16 IF DDI1_DDC_AUX_SEL pulled high I O OD 3 3V HDMI1_CTRLDATA PU 10k 3 3V DDI1_DDC_AUX_SEL D34 Selects the function of ...

Page 31: ...ion of DDI2_CTRLCLK_AUX and DDI2_CTRLDATA_AUX This pin shall have a 1M pull down to logic ground on the Module If this input is floating the AUX pair is used for the DP AUX signals If pulled high the AUX pair contains the CRTLCLK and CTRLDATA signals PD 1M DDI 3 not supported on this product Signal Pin Description I O PU PD Comment DDI3_PAIR0 DDI3_PAIR0 DDI3_PAIR1 DDI3_PAIR1 DDI3_PAIR2 DDI3_PAIR2 ...

Page 32: ...2 DP1_LANE2 TMDS1_DATA0 D33 DDI1_PAIR2 DP1_LANE2 TMDS1_DATA0 D36 DDI1_PAIR3 DP1_LANE3 TMDS1_CLK D37 DDI1_PAIR3 DP1_LANE3 TMDS1_CLK C25 DDI1_PAIR4 C26 DDI1_PAIR4 C29 DDI1_PAIR5 C30 DDI1_PAIR5 C15 DDI1_PAIR6 C16 DDI1_PAIR6 C24 DDI1_HPD DP1_HPD HDMI1_HPD D15 DDI1_CTRLCLK_AUX DP1_AUX HMDI1_CTRLCLK D16 DDI1_CTRLDATA_AUX DP1_AUX HMDI1_CTRLDATA D34 DDI1_DDC_AUX_SEL D39 DDI2_PAIR0 DP2_LANE0 TMDS2_DATA2 D4...

Page 33: ...3 4 5 PCI Express Graphics x16 not supported Signal Pin Description I O PU PD Comment PEG_RX0 PEG_RX0 PEG_RX1 PEG_RX1 PEG_RX2 PEG_RX2 PEG_RX3 PEG_RX3 PEG_RX4 PEG_RX4 PEG_RX5 PEG_RX5 PEG_RX6 PEG_RX6 PEG_RX7 PEG_RX7 PEG_RX8 PEG_RX8 PEG_RX9 PEG_RX9 PEG_RX10 PEG_RX10 PEG_RX11 PEG_RX11 PEG_RX12 PEG_RX12 PEG_RX13 PEG_RX13 PEG_RX14 PEG_RX14 PEG_RX15 PEG_RX15 C52 C53 C55 C56 C58 C59 C61 C62 C65 C66 C68 C6...

Page 34: ...ut Type that is implemented on the module The pins are tied on the module to either ground GND or are no connects NC For Pinout Type 1 these pins are don t care X TYPE2 TYPE1 TYPE0 X X X Pinout Type 1 NC NC NC Pinout Type 2 NC NC GND Pinout Type 3 no IDE NC GND NC Pinout Type 4 no PCI NC GND GND Pinout Type 5 no IDE no PCI GND NC NC Pinout Type 6 no IDE no PCI The Carrier Board should implement co...

Page 35: ... C14 C21 C31 C41 C51 C60 C70 C73 C76 C80 C84 C87 C90 C93 C96 C100 C103 C110 D1 D2 D5 D8 D11 D14 D21 D31 D41 D51 D60 D67 D70 D73 D76 D80 D84 D87 D90 D93 D96 D100 D103 D110 Ground DC power and signal and AC signal return path All available GND connector pins shall be used and tied to carrier board GND plane P ...

Page 36: ...30 Pinouts and Signal Descriptions This page intentionally left blank ...

Page 37: ...le but are not included in the PICMG standard specification 4 1 Connector Switch and LED Locations LED1 4 pin Fan BIOS Defaults RESET Switch LED2 LED3 MIPI60 60 pin to CPU Figure 3 cExpress AL Connector Switch and LED Locations cExpress AL and the DB40 Debug Module For illustration purposes only Figure 4 cExpress AL and the DB40 Debug Module ...

Page 38: ...rovide from COM module 28 BMC Program interface cont d OCD0B Include a jumper to connect OCD0A via 1K0 pull up to 3 3V_BMC 9 GND 29 PWRBTN 10 BIOS_DIS0 30 SYS_RESET 11 RST 31 CB_RESET 12 CLK33_LPC 32 CB_PWROK 13 LPC_FRAME 33 SUS_S3 14 LPC_AD3 34 SUS_S4 15 LPC_AD2 35 Test points SUS_S5 16 LPC_AD1 always power 3 3V provide from COM module 36 POSTWDT_DI S Connect to Jumper for Debug 17 LPC Bus LPC_AD...

Page 39: ...SET see 5 1 4 Exception Codes LED2 Green Power Source 3Vcc S0 LED ON S3 S4 S5 LED OFF ECO mode LED OFF LED3 Red BMC output and same signal as WDT B27 on BtB connector Module power up WD LED LED OFF Watchdog counting WD LED Keep Last State Watchdog timed out WD LED LED ON Watchdog RESET WD LED LED ON Rebooted after WD RESET WD LED LED ON Rebooted after PWRBTN WD LED LED OFF Rebooted after RESET BTN...

Page 40: ... PTI_0_DATA 1 22 PTI_1_DATA 2 23 PTI_0_DATA 2 24 PTI_1_DATA 3 25 PTI_0_DATA 3 26 No Connect 27 PTI_0_DATA 4 28 No Connect 29 PTI_0_DATA 5 30 No Connect 31 PTI_0_DATA 6 32 No Connect 33 PTI_0_DATA 7 34 Reset Out 35 No Connect 36 Boot Stall 37 No Connect 38 CPU Boot Stall 39 No Connect 40 Power Button 41 No Connect 42 PWRGOOD 43 No Connect 44 No Connect 45 No Connect 46 No Connect 47 No Connect 48 I...

Page 41: ...ess AL Module Interfaces 35 4 5 Fan Connector Connector Type JVE 24W1125A 04M00 Pin Orientation 1 2 3 4 Pin Assignment Name Signal 1 FAN_PWMOUT 2 FAN_TACHIN 3 Ground 4 5V Table 5 Fan Connector Pin Definition ...

Page 42: ...orm the following steps 1 Shut down the system 2 Press the BIOS Setup Defaults RESET Button continuously and boot up the system You can release the button when the BIOS prompt screen appears 3 The BIOS prompt screen will display a confirmation that BIOS defaults have been reset and request that you reboot the system ...

Page 43: ... be placed in the SPI0 slot on the carrier In dual BIOS Failsafe mode both BIOS chips on the module are configured as SPI1 Only one of the two is connected to the SPI bus at any given time In case of failure of the primary SPI1 BIOS the system will reboot and switch to the secondary SPI1 BIOS on the module In Failsafe mode the SPI0 BIOS socket on the carrier can be populated In either mode BIOS Se...

Page 44: ...38 Module Interfaces This page intentionally left blank ...

Page 45: ...he number of boot attempts Watchdog Timer Set Reset Disable Watchdog Timer Features auto reload at power up System Restart Cause Power loss BIOS Fail Watchdog Internal Reset External Reset Fail safe BIOS support In case of a boot failure hardware signals tells external logic to boot from fail safe BIOS Flash area 1kB Flash area for customer data 2K Bytes Protected Flash area Keys IDs etc can be st...

Page 46: ...rt MSB 8 LSB x 3 3 1024 Table 7 SEMA Onboard Voltage Monitor 5 1 2 Main Current The BMC of the cExpress AL implements a current monitor The current can be read by calling the SEMA function Get Main Current The function returns four 16 bit values divided in high byte MSB and low byte LSB These 4 values represent the last 4 currents drawn by the board The values are sampled every 250ms The order of ...

Page 47: ... Code Error Message 0 NOERROR 2 NO_SUSCLK 3 NO_SLP_S4_S5 4 NO_SLP_S3 5 BIOS_FAIL 6 RESET_FAIL 7 RESETIN_FAIL 8 NO_CB_PWRGD 9 CRITICAL_TEMP 10 POWER_FAIL 11 VOLTAGE_FAIL 12 NO_3V3_5V_A_PG 13 NO_VNN_PG 14 NO_1V24_A_PG 15 NO_VDDQ_PG 16 NO_V1P05S_PG 17 NO_SYS_GD 18 NO_V12 19 MEMORY_ERROR 20 NO_P3V3_A_READY Table 9 SEMA Exception Codes 5 1 5 BMC Flags The BMC Flags register returns the last detected Ex...

Page 48: ...42 Smart Embedded Management Agent SEMA This page intentionally left blank ...

Page 49: ...interrupt 028h 029h P2SB ITSS interrupt 02Ch 02Dh P2SB ITSS interrupt 02Eh 02Fh P2SB LPC eSPI 030h 031h P2SB ITSS interrupt 034h 035h P2SB ITSS interrupt 038h 039h P2SB ITSS interrupt 03Ch 03Dh P2SB ITSS interrupt 040h P2SB ITSS Timer 0 Register 041h P2SB Terminate 042h P2SB ITSS Timer 2 Register 043h P2SB ITSS Timer Control Word Register 04Eh 04Fh LPC eSPI LPC eSPI 050h P2SB ITSS alias of 040h 05...

Page 50: ...086h P2SB LPC eSPI or PMC 087h P2SB Terminate 088h P2SB LPC eSPI or PMC 089h 08Bh P2SB Terminate 08Ch 08Eh P2SB LPC eSPI or PMC 08Fh P2SB Terminate 090h P2SB LPC eSPI 091h P2SB Terminate 092h P2SB ITSS CPU I F 093h P2SB Terminate 094h 096h P2SB LPC eSPI or PMC 097h P2SB Terminate 098h P2SB LPC eSPI or PMC 099h 09Bh P2SB Terminate 09Ch 09Eh P2SB LPC eSPI or PMC 09Fh P2SB Terminate 0A0h 0A1h P2SB IT...

Page 51: ...ailable 0 Counter 0 N A No 1 Keyboard controller IRQ1 via SERIRQ No 2 Cascade interrupt from slave PIC N A No 3 Serial Port 4 COM3 IRQ3 via SERIRQ PIRQ Note 1 4 Serial Port 3 COM4 IRQ4 via SERIRQ PIRQ Note 1 5 Generic IRQ5 via SERIRQ PIRQ Note 1 6 Generic IRQ6 via SERIRQ PIRQ No 7 Generic IRQ7 via SERIRQ PIRQ Note 1 8 Real time clock N A No 9 Generic N A Note 1 10 Serial Port 1 COM1 IRQ10 via SERI...

Page 52: ...OM2 IRQ11 via SERIRQ Note 1 12 PS 2 Mouse IRQ12 via SERIRQ Note 1 13 FERR logic N A Note 1 14 SATA Primary IRQ14 via SERIRQ Note 1 15 SATA Secondary IRQ15 via SERIRQ Note 1 16 N A P E G Root Port Intel HDA PCIE Port 0 1 2 3 4 5 6 EHCI Conterller 2 I G D XHCI Controller Note 1 17 N A PCIE Port 0 1 2 3 4 5 6 P E G Root Port Note 1 18 N A PCIE Port 0 1 2 3 4 5 6 P E G Root Port SMBus Controller EHCI ...

Page 53: ...3 0 PMC 0 13 1 SPI 0 13 2 Shared SRAM 0 13 3 Audio 0 14 0 CSE HECI1 0 15 0 CSE HECI2 0 15 1 CSE HECI3 0 15 2 CSE fTPM PSF ghost 0 15 7 CSE HOFFL 0 16 0 ISH 0 17 0 SATA 0 18 0 PCIe A 0 0 19 0 PCIe A 1 0 19 1 PCIe A 2 0 19 2 PCIe A 3 0 19 3 PCIe B 0 0 20 0 PCIe B 1 0 20 1 USB Host xHCI 0 21 0 USB Device xDCI 0 21 1 I2C 0 0 22 0 I2C 1 0 22 1 I2C 2 0 22 2 I2C 3 0 22 3 CSE I2C 6 7 access 0 22 6 CSE SSR...

Page 54: ...Bus Device Function I2C 5 0 23 1 I2C 6 0 23 2 I2C 7 0 23 3 UART 0 0 24 0 UART 1 0 24 1 UART 2 0 24 2 UART 3 0 24 3 SPI 0 0 25 0 SPI 1 0 25 1 SPI 2 0 25 2 PWM 0 26 0 SD Card 0 27 0 eMMC 0 28 0 UFS 0 29 0 SDIO 0 30 0 LPC 0 31 0 SMBUS 0 31 1 ...

Page 55: ...TC 22 INTD 23 Int3 INTD 21 INTA 22 INTB 21 INTC 22 INTD 23 INTA 20 INT Line SMBus Controller NPK Device IUNT PMC HD Audio CES ISH SATA Controller XHCI XDCI Int0 INTA 16 INTF 21 INTA 40 INTA 25 INTE 20 INTE 26 INTA 19 INTB 17 Int1 INTE 20 INTC 13 Int2 Int3 INT Line I2C0 I2C1 I2C2 I2C3 I2C4 I2C5 I2C6 I2C7 SPI1 Int0 INTA 27 INTF 31 INTA 35 Int1 INTB 28 INTB 32 Int2 INTC 29 INTC 33 Int3 INTD 30 INTD 3...

Page 56: ...50 System Resources 6 6 SMBus Address Table Device Address DIMMA A0h DIMMB A4h BMC 50h Extend GPIO 40h I210 49h USB2514BI 58h LM73 92h PEX8605 B7h C1h NXP eDP to LVDS transmitter C0h ...

Page 57: ... Information System Information Board Information System Date and Time Access Level CPU Configuration Graphics Configuration Power Management System Management Thermal Management Watchdog Timer CSM Configuration Super IO Configuration Serial Console Redirection USB Network Miscellaneous Driver Health Trusted Computing AMI Graphic Output Protocol Policy SDIO Configuration North Bridge South Bridge ...

Page 58: ...stalled Memory Size Memory Frequency Info only Display Memory Frequency SOC SKU Info only Display SOC SKU Version 7 2 3 Main Board Information Feature Options Description Board Information Submenu Board Information Info only Serial Number Info only Display SEMA serial Number Manufacturing Date Info only Display SEMA manufacturing date Last Repair Date Info only Display SEMA last repair date MAC ID...

Page 59: ... a HW or SW Reset or after a successful power up Boot Reason Info only The boot reason is the event which causes the reboot of the system 7 2 4 Main System Date Time Feature Options Description System Date Info only System Time Info only 7 2 5 Main Access Level Feature Options Description Access Level Info only ...

Page 60: ...y cache info L1 Code Cache Info only Display cache info L2 Cache Info only Display cache info L3 Cache Inf o only Display cache info Speed Info only Display CPU Speed 64 bit Info only Display 64 bit Support CPU Power Management Submenu CPU Power Management options CPU Power Management Configuration Info only EIST Disabled Enabled Enable Disable Intel SpeedStep Burst Mode Disabled Enabled Enable Di...

Page 61: ...wer Limit 1 Info Only Display Power Limit 1 Power Watts Power Limit 1 Clamp Mode Disabled Enabled Enable Disable Power Limit 1 Clamp Mode Power Limit 1 Power Auto 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Power Limit 1 in Watts Auto will program Power Limit 1 based on silicon default support value Power Limit 1 Time Windows Auto 1 2 3 4 5 6 7 8 10 12 14 16 20 24 28 Power Limit 1 Time...

Page 62: ...d Enable Disable Thermal Monitor Monitor Mwait Disabled Enabled Auto Enable Disable Monitor Mwait P STATE Coordination HW_ALL SW_ALL SW_ANY Change P STATE Coordination type DTS Disabled Enabled Enable Disable Digital Thermal Sensor 7 3 2 Advanced Graphics Configuration Feature Options Description Graphics Configuration Info only LVDS Info only Data format and Color Depth VESA 24 bpp JEIDA 24 bbp J...

Page 63: ...bled Enables or Disables Lock of Legacy Resources LID Function Disabled Enabled Enable Disable LID Function ECO Mode Disabled Enabled Reduces the power consumption of the system but after a shutdown you have to wait at least 5 seconds before you can restart the system Power Consumption Submenu Power Consumption 7 3 3 1 Advanced Power Management Power Consumption Feature Options Description Power C...

Page 64: ...ration Parameters Info Only Thermal and Fan Speed Submenu Smart Fan Submenu Critical Trip Point Disabled 80 C 90 C 95 C 105 C The value is the temperature threshold of the Critical Trip Point Passive Cooling Trip Point Disabled 70 C 80 C 90 C 100 C The value is the temperature threshold of the Passive Cooling Trip Point 7 3 5 1 Advanced Thermal Management Thermal and Fan Speed Feature Options Desc...

Page 65: ... Module Configuration Info only CSM Support Disableed Enabled Enabled Disabled CSM Support 7 3 8 Advanced Super IO Configuration Feature Options Description NCT5104D Info only Serial Port 1 Configuration Submenu Set Parameters of Serial Port 1 COMA Serial Port 2 Configuration Submenu Set Parameters of Serial Port 2 COMB W83627DHG Info Only Serial Port 1 Configuration Submenu Set Parameters of Seri...

Page 66: ...gs Info Only Display IO IRQ information of COM Port Change Settings Auto IO 248h IRQ 11 IO 240h IRQ 3 4 5 6 7 10 11 12 IO 248h IRQ 3 4 5 6 7 10 11 12 IO 250h IRQ 3 4 5 6 7 10 11 12 IO 258h IRQ 3 4 5 6 7 10 11 12 Select an optimal setting for Super IO Device 7 3 8 3 Advanced Super IO Configuration Serial Port 1 Configuration W83627DHG Feature Options Description Serial Port 1 Configuration Submenu ...

Page 67: ...n Settings Submenu The settings specify how the host computer and the remote computer which the user is using will exchange data Both computers should have the same or compatible settings The item will be lunched before enable Console Redirection COM2 Info only Console Redirection Enabled Disabled Console Redirection Enable or Disable Console Redirection Settings Submenu The settings specify how t...

Page 68: ...rial port transmission speed The speed must be matched on the other side Long or noisy lines may require lower speeds Data Bits 7 8 Data Bits Parity None Even Odd Mark Space A parity bit can be sent with the data bits to detect some transmission errors Even parity bit is 0 if the num of 1 s in the data bits is even Odd parity bit is 0 if num of 1 s in the data bits is odd Mark parity bit is always...

Page 69: ...T100 Extends VT100 to support color function keys etc VT UTF8 Uses UTF8 encoding to map Unicode chars onto 1 or more bytes Bits per second 9600 19200 38400 57600 115200 Selects serial port transmission speed The speed must be matched on the other side Long or noisy lines may require lower speeds Data Bits 7 8 Data Bits Parity None Even Odd Mark Space A parity bit can be sent with the data bits to ...

Page 70: ...Settings Info only Teriminal Type VT100 VT100 VT UTF8 ANSI Emulation ANSI Extended ASCII char set VT100 ASCII char set VT100 Extends VT100 to support color function keys etc VT UTF8 Uses UTF8 encoding to map Unicode chars onto 1 or more bytes Bits per second 9600 19200 38400 57600 115200 Selects serial port transmission speed The speed must be matched on the other side Long or noisy lines may requ...

Page 71: ...t to Always Enable 7 3 9 4 Advanced Serial Console Redirection Console Redirection Settings if COM4 enabled Feature Options Description COM4 Info only Console Redirection Settings Info only Teriminal Type VT100 VT100 VT UTF8 ANSI Emulation ANSI Extended ASCII char set VT100 ASCII char set VT100 Extends VT100 to support color function keys etc VT UTF8 Uses UTF8 encoding to map Unicode chars onto 1 ...

Page 72: ...er is selected then Legacy Console Redirection is disabled before booting to legacy OS When Always Enable is selected then Legacy Console Redirection is enabled for legacy OS Default setting for this option is set to Always Enable 7 3 9 5 Advanced Serial Console Redirection Legacy Console Redirection Settings Feature Options Description Legacy Serial Redirection Port COM1 COM2 COM3 COM4 Select a C...

Page 73: ...Lan controller Network Stack Disable Enable Enable Disable UEFI Network Stack 7 3 12 Advanced Miscellaneous Feature Options Description Miscellanous Info Only Control the PCI Express Root Port Smart Battery Function Disable Enable Enable Disable Battery Function 7 3 13 Advanced Driver Health Feature Options Description Driver Name Info only Provides Health Status for the Drivers Controllers 7 3 14...

Page 74: ...ced AMI Graphic Output Protocol Policy Feature Options Description Intel R Graphics Controller Info Only Intel R GOP Driver Info Only Output Select DVI Output Interface 7 3 16 Advanced SDIO Configuration Feature Options Description SDIO Configuration Info Only SD Card GPIO MODE GPIO SD Card Select SD Card or GPIO function SDIO Access Mode Auto ADMA SDMA PIO Auto Option Access SD device in DMA mode...

Page 75: ...ptions Description Serial IRQ Mode Quiet Continuous Configure Serial IRQ Mode SMBus Support Disable Enable Enable Disable SMBus Support OS Selection Windows Android Win7 Intel Linux Select the target OS PCI CLOCK RUN Disable Enable Enables CLKRUN logic to stop PCI clocks 7 4 3 Chipset Uncore Configuration Feature Options Description GOP Configuration Info only Active LFP Config No LFP eDP LVDS Act...

Page 76: ...Integerated Graphics Devices Disable Enable Enable Enable Integrated Graphics Device IGD when selected as the Primary Video Adaptor Disable Always disable IGD Primary Display IGD PCIe HG Select which of IGD PCI Graphics device should be Primary Display Aperture Size 128MB 256MB 512MB Select the Aperture Size DVMT Pre Allocated 64M 96M 128M 160M 192M 224M 256M 288M 320M 352M 384M 416M 448M 480M 512...

Page 77: ...omplicace Mode Enable Disable PCIE Port 1 4 Configuration 4x1 Port 1x2 2x1 Port 2x2 Port 1x4 Port To configure PCI E Port 1 4 of PCH 4X1 Port 1 4 x1 and Port 8 x1 1x2 2x1 Port 1 x2 Port 2 disabled Ports 3 and Port 4 x1 2x2 Port 1 2 x2 and Port 3 4 x2 1x4 Port 1 x4 Ports 2 4 disabled PCI ExpressRoot Port 1 Submenu Control the PCI Express Root Port AUTO To disable unused root port automatically for ...

Page 78: ...ng Enable Disable CER Disable Enable PCI Express Device Correctable Error Reporting Enable Disable CTO Default Setting 16 15 ms 65 210 ms 260 900 ms 1 3 5 s Disable PCI Express Completion Timer TO Enable Disable SEFE Disable Enable Root PCI Express System Error on Fatal Error Enable Disable SENFE Disable Enable Root PCI Express System Error on Non Fatal Error Enable Disable SECE Disable Enable Roo...

Page 79: ...le Auto Control the PCI Express Root Port AUTO To disable unused root port automatically for the most optimum power savings Enable Enable PCIe root port Disable Disable PCIe root port ASPM Disable Enable PCI Express Active State Power Management settings L1 Substates Disable L1 1 L1 2 L1 1 L1 2 PCI Express L1 Substates settings ACS Disable Enable Enable Disable Access Control Services Extended Cap...

Page 80: ...oop Latency Override for PCH PCIE Disabled Disable override Manual Manually enter override values Auto default Maintain default BIOS flow PCIE LTR Lock Disable Enable PCIE LTR Configuration Lock PCIe Selection De0emphasis Disable Enable When the Link is operating at 5 0 GT s speed this bit selects the level of de emphasis for an Upstream component 1b 3 5 dB 0b 6 dB Chipset South Cluster Configurat...

Page 81: ...itter Half Swing Enable Disable Extra Bus Reserved 0 Extra Bus Reserved 0 7 for bridges behind this Root Bridge Reserved Memory 10 Reserved Memory and Prefetchable Memory 1 20MB Range for this Root Bridge Reserved I O 4 Reserved I O 4K 8K 12K 16K 20K Range for this Root Bridge PCH PCIe LTR Configuration Info only PCH PCIE LTR Disable Enable PCH PCIE Latency Reporting Enable Disable Snoop Latency O...

Page 82: ...ng Enable Disable CER Disable Enable PCI Express Device Correctable Error Reporting Enable Disable CTO Default Setting 16 15 ms 65 210 ms 260 900 ms 1 3 5 s Disable PCI Express Completion Timer TO Enable Disable SEFE Disable Enable Root PCI Express System Error on Fatal Error Enable Disable SENFE Disable Enable Root PCI Express System Error on Non Fatal Error Enable Disable SECE Disable Enable Roo...

Page 83: ...Controller The Chipset SATA controller supports the 2 black internal SATA ports up to 3Gb s supported per port SATA Mode Selection AHCI Determines how SATA controller s operate SATA Interface Speed Gen1 Gen2 Gen3 Select SATA Interface Speed CHV A1 always with Gen Speed SATA Test Mode Disable Enable Test Mode Enable Disable Aggressive LPM Support Disable Enable Enable PCH to Aggressively enter link...

Page 84: ...d Spin Up will be performed and only the drives which have this option enabled will spin up at boot Otherwise all drives spin up at boot SATA Device Type Hard Disk Drive Solid State Drive Identify the SATA port is connected to Solid State Drive or Hard Disk Drive SATA Port 1 DevSlp Disabled Enabled Enable Disable SATA Port 1 DevSlp Board rework for LP needed before enable DITO Configuration Disabl...

Page 85: ...ively Enable Disable the corresponding USB port from reporting a Device Connection to the controller 7 4 4 6 Chipset South Cluster Configuration Miscellaneous Configuration Feature Options Description Miscellaneous Configuration Info only State After G3 S0 State S5 State Last State Specify what state to go to when power is re applied after a power failure G3 state S0 State System will boot directl...

Page 86: ...t 1 Number of seconds to wait for setup activation key 65535 0xFFFF means indefinite waiting Bootup NumLock State On Off Select the keyboard Number state Ouiet Boot Disabled Enabled Select the keyboard NumLock state Fast Boot Disabled Enabled Enable or Disable FastBoot features Most probes are skipped to reduce time cost during boot New Boot Option Policy Default Place First Place Last Controls th...

Page 87: ...system setup after saving the changes Discard Changes and Exit Exit system setup without saving any changes Save Change and Reset Reset the system after saving the changes Discard Changes and Reset Reset system setup without saving any changes Save Options Info only Save Changes Save Changes done so far to any of the setup options Save as User Defaults Save the changes done so far as User Defaults...

Page 88: ...82 BIOS Setup This page intentionally left blank ...

Page 89: ...d by the Intel Platform Innovation Framework for EFI the Framework The Framework refers the following boot phases which may apply to various status code checkpoint descriptions Security SEC initial low level initialization Pre EFI Initialization PEI memory initialization1 Driver Execution Environment DXE main hardware initialization2 Boot Device Selection BDS system setup pre OS user interface sel...

Page 90: ...covery errors PEI 8 2 Standard Status Codes 8 2 1 SEC Phase Status Code Description 0x00 Not used Progress Codes 0x01 Power on Reset type detection soft hard 0x02 AP initialization before microcode loading 0x03 North Bridge initialization before microcode loading 0x04 South Bridge initialization before microcode loading 0x05 OEM initialization before microcode loading 0x06 Microcode loading 0x07 A...

Page 91: ...th Bridge initialization North Bridge module specific 0x19 Pre memory South Bridge initialization is started 0x1A Pre memory South Bridge initialization South Bridge module specific 0x1B Pre memory South Bridge initialization South Bridge module specific 0x1C Pre memory South Bridge initialization South Bridge module specific 0x1D 0x2A OEM pre memory initialization codes 0x2B Memory initialization...

Page 92: ...dge module specific 0x3F 0x4E OEM post memory initialization codes 0x4F DXE IPL is started PEI Error Codes 0x50 Memory initialization error Invalid memory type or incompatible memory speed 0x51 Memory initialization error SPD reading has failed 0x52 Memory initialization error Invalid memory size or memory modules do not match 0x53 Memory initialization error No usable memory detected 0x54 Unspeci...

Page 93: ...rocess started 0xF3 Recovery firmware image is found 0xF4 Recovery firmware image is loaded 0xF5 0xF7 Reserved for future AMI progress codes Recovery Error Codes 0xF8 Recovery PPI is not available 0xF9 Recovery capsule is not found 0xFA Invalid recovery capsule 0xFB 0xFF Reserved for future AMI error codes 8 2 4 PEI Beep Codes of Beeps Description 1 Memory not Installed 1 Memory was installed twic...

Page 94: ...pecific 0x6E North Bridge DXE initialization North Bridge module specific 0x6F North Bridge DXE initialization North Bridge module specific 0x70 South Bridge DXE initialization is started 0x71 South Bridge DXE SMM initialization is started 0x72 South Bridge devices initialization 0x73 South Bridge DXE Initialization South Bridge module specific 0x74 South Bridge DXE Initialization South Bridge mod...

Page 95: ...0xA3 IDE Enable 0xA4 SCSI initialization is started 0xA5 SCSI Reset 0xA6 SCSI Detect 0xA7 SCSI Enable 0xA8 Setup Verifying Password 0xA9 Start of Setup 0xAA Reserved for ASL see ASL Status Codes section below 0xAB Setup Input Wait 0xAC Reserved for ASL see ASL Status Codes section below 0xAD Ready To Boot event 0xAE Legacy Boot event 0xAF Exit Boot Services event 0xB0 Runtime Set Virtual Address M...

Page 96: ...Error loading Boot Option LoadImage returned error 0xDA Boot Option is failed StartImage returned error 0xDB Flash update is failed 0xDC Reset protocol is not available 8 2 6 DXE Beep Codes of Beeps Description 1 Invalid password 4 Some of the Architectural Protocols are not available 5 No Console Output Devices are found 5 No Console Input Devices are found 6 Flash update is failed 7 Reset protoc...

Page 97: ...ransitioned into ACPI mode Interrupt controller is in PIC mode 0xAA System has transitioned into ACPI mode Interrupt controller is in APIC mode 8 3 OEM Reserved Checkpoint Ranges Status Code Description 0x05 OEM SEC initialization before microcode loading 0x0A OEM SEC initialization after microcode loading 0x1D 0x2A OEM pre memory initialization codes 0x3F 0x4E OEM PEI post memory initialization c...

Page 98: ...92 BIOS Checkpoints Beep Codes This page intentionally left blank ...

Page 99: ... to board connector with 0 5mm for a stacking height of 5 mm This connector can be used with 5 mm through hole standoffs SMT type Tyco 3 6318491 6 Foxconn QT002206 4141 3H 220 pin board to board connector with 0 5mm for a stacking height of 8 mm This connector can be used with 8 mm through hole standoffs SMT type Common Specifications Current capacity 0 5A per pin Rated voltage 50 VAC Insulation r...

Page 100: ... with all COM Express modules 9 2 2 Heat Sinks A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless depending on the thermal requirements 9 2 3 Installation Install a heat spreader or heat sink using the following instructions Step 1 Before mounting the heatsink install the required memory modules onto the SODIMM socket s on the COM Expre...

Page 101: ...asten the heatsink to the module Step 4 Place the COM Express module and heatsink assembly onto the connectors on the carrier board as shown Then press down on the module until it is firmly seated on the carrier board Step 5 Use the five M2 5 L 16mm screws provided to secure the COM Express module to the carrier board from the solder side ...

Page 102: ...96 Mechanical Information Step 6 If you are installing a heatsink with a fan plug the fan connector into the carrier board as shown ...

Page 103: ...the choice of 5 mm or 8mm board to board connectors there is the choice of Top and Bottom mounting In Top mounting the threaded standoffs are on the carrier board and the thermal solution is equipped with through hole standoffs In Bottom mounting the threaded standoffs are on the thermal solution and the carrier board has through hole standoffs Figure 6 COM Express Mounting Methods ...

Page 104: ...offs are DIP type and through hole standoffs are SMT type Other types not listed are available upon request 5mm through hole standoff SMT type P N 33 72000 0050 5mm threaded standoff DIP type P N 33 72016 0050 8mm through hole standoff SMT type P N 33 72000 0080 8mm threaded standoff DIP type P N 33 72015 0050 Figure 7 COM Express Standoff Types ...

Page 105: ...bles To avoid electrical shock and or damage to equipment Keep equipment away from water or liquid sources Keep equipment away from high heat or high humidity Keep equipment properly ventilated do not block or cover ventilation openings Make sure to use recommended voltage and power source settings Always install and operate equipment near an easily accessible electrical socket outlet Secure the p...

Page 106: ...0200 Toll Free 1 800 966 5200 USA only Fax 1 408 360 0222 Email info adlinktech com ADLINK Technology China Co Ltd Address 300 Fang Chun Rd Zhangjiang Hi Tech Park Pudong New Area Shanghai 201203 China Tel 86 21 5132 8988 Fax 86 21 5132 3588 Email market adlinktech com LiPPERT ADLINK Technology GmbH Address Hans Thoma Strasse 11 D 68163 Mannheim Germany Tel 49 621 43214 0 Fax 49 621 43214 30 Email...

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