ADLINK Technology cExpress-AL, User Manual

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cExpress-AL
Pinouts and Signal Descriptions
13
3.3. AB Signal Descriptions
3.3.1. Audio Signals
Signal Pin Description I/O PU/PD Comment
HDA_RST# A30 Reset output to CODEC, active low. O 3.3V
HDA_SYNC A29 Sample-synchronization signal to the
CODEC(s). O 3.3V
HDA_BITCLK A32 Serial data clock generated by the
external CODEC(s).
I/O 3.3V
HDA_SDOUT A33 Serial TDM data output to the CODEC. O 3.3V
HDA_SDIN[2:0] B28
B30 Serial TDM data inputs from up to 3
CODECs. I/O 3.3V PD 680
ohm Only supports HDA_SDIN0.
PD 680 ohm, based on SoC
vendor guidance.
3.3.2. Analog VGA (build option)
Signal Pin Description I/O PU/PD Comment
VGA_RED B89 Red for monitor.
Analog DAC output, designed to
drive a 37.5-Ohm equivalent load. O Analog PD 150R
VGA_GRN B91 Green for monitor
Analog DAC output, designed to
drive a 37.5-Ohm equivalent load. O Analog PD 150R
VGA_BLU B92 Blue for monitor.
Analog DAC output, designed to
drive a 37.5-Ohm equivalent load. O Analog PD 150R
VGA_HSYNC B93 Horizontal sync output to VGA
monitor
O 3.3V
VGA_VSYNC B94 Vertical sync output to VGA monitor O 3.3V
VGA_I2C_CK B95 DDC clock line (I²C port dedicated
to identify VGA monitor capabilities)
I/O OD 3.3V PU 2k2
3.3V
VGA_I2C_DAT B96 DDC data line. I/O OD 3.3V PU 2k2
3.3V
VGA is by build option, in
place of DDI 2