Actel IGLOO PLUS Starter Kit, User Manual, Page: 34 / 62

Operation of Board Components
34 IGLOO PLUS Starter Kit User’s Guide
Flash*Freeze Switch
An F*F switch is provided on the board for designs that utilize the Flash*Freeze technology. Setting the F*F switch to
FF_ON will enable the Flash*Freeze mode of the IGLOO PLUS device. Since the Schmitt Trigger chip (U12) is NOT
populated on-board for the F*F switch, the Schmitt Trigger feature should be enabled in the FPGA design for the
Flash*Freeze input to enhance noise immunity (
Figure 4-8 ). The Schmitt Trigger is an advanced I/O feature of the
IGLOO PLUS FPGA family. If the IGLOO PLUS FPGA is swapped out with a device that does not have the
advanced Schmitt Trigger I/O feature, the Schmitt Trigger chip (U12) should be populated
.
Figure 4-8 · Flash*Freeze Schematic, Schmitt Triggered
Some features on this board are included to demonstrate the Flash*Freeze variants of the IGLOO PLUS FPGA. I/Os
can be individually configured to either hold their previous state or be tristated during Flash*Freeze mode. Alternatively,
they can be set to a certain state (high or low) using weak pull-up or pull-down I/O attribute configurations. These
Flash*Freeze variants can be demonstrated by configuring the I/Os in Designer and using switches as inputs to control
the FET LEDs. Refer to the demo design, which provides additional details on demonstrating these Flash*Freeze
variants (
“IGLOO PLUS Board Demo” on page 51 ).
Output Enabled "Don't care" Weak pull to hold state
Disabled Enabled Weak pull-up/pull-down
Disabled Disabled Tristate
Bidirectional /
Tristate Buffer
E = 0
(input/tristate)
Enabled Enabled Weak pull-up/pull-down
1
Disabled Enabled Weak pull-up/pull-down
2
Enabled Disabled Tristate
1
Disabled Disabled Tristate
2
E = 1 (output)
Enabled "Don't care" Weak pull to hold state
3
Disabled Enabled Weak pull-up/pull-down
Disabled Disabled Tristate
Table 4-2 · IGLOO PLUS Flash*Freeze Mode (type 1 and type 2)—I/O Pad State (continued)
Buffer Type Hold State
I/O Pad
Weak Pull-Up/-Down
I/O Pad State in
Flash*Freeze Mode
Notes:
1. Internal core logic driven by this input buffer will be set to the value this I/O had when entering Flash*Freeze mode.
2. Internal core logic driven by this input buffer will be tied High as long as the device is in Flash*Freeze mode.
3. For bidirectional buffers: Internal core logic driven by the input portion of the bidirectional buffer will be set to the hold state.
V3P3
V3P3
IGLOO_FF [4]
Mfr P/N :AYZ0102AGRL
Mfr: ITT INDUSTRIES
R61
10K R61
10K
2
1
3
SW8
AYZ0102AGRL
SW8
AYZ0102AGRL
+
C64
10uF
+
C64
10uF
C63
0.1uF
C63
0.1uF
R52
0
R52
0
C61 0.1uF C61 0.1uF
NC
1
A
2
GND
3
VCC
5
Y
4
U12
DNP
Mfg P/N = SN74AUP1G17DCKR
Manufacturer = TI
U12
DNP
Mfg P/N = SN74AUP1G17DCKR
Manufacturer = TI
+
C62
2.2uF
+
C62
2.2uF
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