Operation of Board Components
32
IGLOO PLUS Starter Kit User’s Guide
Flash*Freeze Type 2: Control by Dedicated Flash*Freeze Pin and Internal Logic
The device can be made to enter Flash*Freeze mode by activating the FF pin together with Actel's Flash*Freeze
management IP core or user-defined control logic (
Figure 4-6
) within the FPGA core. This method enables the design
to perform important activities before allowing the device to enter Flash*Freeze mode, such as transitioning into a safe
state, completing the processing of a critical event. Designers are encouraged to take advantage of Actel's Flash*Freeze
Management IP to handle clean entry and exit of Flash*Freeze mode. The device will only enter Flash*Freeze mode
when the Flash*Freeze pin is asserted (active low) and the User Low Static ICC (ULSICC) macro input signal, called
the LSICC signal, is asserted (high). One condition is not sufficient to enter Flash*Freeze mode type 2; both the FF pin
and LSICC signal must be asserted.
Figure 4-7
shows the timing diagram for entering and exiting Flash*Freeze mode type 2. After exiting Flash*Freeze
mode type 2 by deasserting the Flash*Freeze pin, the LSICC signal must be deasserted by the user design. This will
prevent entering Flash*Freeze mode by asserting the Flash*Freeze pin only. Refer to
Table 4-1 on page 33
for
Flash*Freeze (FF) pin and LSICC signal assertion and deassertion values.
Figure 4-6 · Flash*Freeze Mode Type 2 – Controlled by Flash*Freeze Pin and Internal Logic (LSICC signal)
Figure 4-7 · Flash*Freeze Mode Type 2 – Timing Diagram
INBUF_FF
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LSICC Signal
Normal
Operation
Flash*Freeze
Mode
Normal
Operation
Flash*Freeze Pin
t = 1 µs
t = 1 µs
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Summary of Contents for IGLOO PLUS Starter Kit
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