
Flash*Freeze Mode
IGLOO PLUS Starter Kit User’s Guide
31
Flash*Freeze Types
Type 1: Control by dedicated Flash*Freeze Pin.
Type 2: Control by dedicated Flash*Freeze Pin and Internal Logic.
Flash*Freeze Type 1: Control by Dedicated Flash*Freeze Pin
Flash*Freeze type 1 is intended for systems where either the device will be reset upon exiting Flash*Freeze mode, or data
and clock are managed externally. The device enters Flash*Freeze mode 1 μs after the dedicated FF pin is asserted (active
low), and returns to normal operation when the FF pin is deasserted (high). In this mode, FF pin assertion or
deassertion is the only condition that determines entering or exiting Flash*Freeze mode (
Figure 4-4
). An INBUF_FF I/
O buffer macro must be used to identify the Flash*Freeze input in your design.
Figure 4-4 · Flash*Freeze Mode Type 1 – Controlled by the Flash*Freeze Pin
Figure 4-5 · Flash*Freeze Mode Type 1 – Timing Diagram
User Design
Actel IGLOO, IGLOO PLUS, IGLOO nano,
ProASIC3L, or RT ProASIC3 Device
Flash*Freeze
Mode
Enables Entering
Flash*Freeze Mode
Flash*Freeze
Signal
Flash*Freeze
Technology
Flash*Freeze (FF) Pin
INBUF_FF
Flash*Freeze
Mode Control
AND
To FPGA Core or Floating
1
Normal
Operation
Flash*Freeze
Mode
Normal
Operation
Flash*Freeze Pin
t = 1 µs
t = 1 µs
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