Actel IGLOO PLUS Starter Kit, User Manual, Page: 30 / 62

Operation of Board Components
30 IGLOO PLUS Starter Kit User’s Guide
Schematic
Figure 4-2 shows the schematic for reset.
Figure 4-2 · Reset Schematic
Flash*Freeze Mode
The IGLOO PLUS device has an ultra-low-power static mode, called Flash*Freeze mode, which
retains all SRAM
and register information and can still quickly return to normal operation ( Figure 4-3 ).
Flash*Freeze technology enables the user to quickly (within 1 μs) enter and exit Flash*Freeze mode by activating the
Flash*Freeze pin while all power supplies are kept at their original values. I/Os, global I/Os, and clocks can still be
driven and can be toggling without impact on power consumption, and the device retains all core registers, SRAM
information, and I/O states. I/Os can be individually configured to either hold their previous state or can be tristated
during Flash*Freeze mode.
There are two ways to use Flash*Freeze mode. In Flash*Freeze type 1, entering and exiting the mode is exclusively
controlled by the assertion and deassertion of the FF pin. This enables an external processor or human interface device to
directly control Flash*Freeze mode. In Flash*Freeze mode type 2, entering and exiting the mode is controlled by both
the FF pin AND user-defined logic. Flash*Freeze management IP can be used in type 2 mode for clock and data
management while entering and exiting Flash*Freeze mode.
For more information and detailed usage of Flash*Freeze modes, refer to the “Actel’s Flash*Freeze Technology and Low
Power Modes” chapter of the
IGLOO PLUS FPGA Fabric User’s Guide
.
V3P3
V3P3
PBRESET_N [4]
Mfr P/N :KSC403J 50SH LFG
Mfr:ITT INDUSTRIES
Mfr P/N :DS1818R-20+T&R
Mfr: Dallas
RST
C65
0.1uF
C65
0.1uF
VCC
2
GND
3
RST
1
U13
DNP
U13
DNP
R63
0
R63
0
1 2
3 4
SW7
KSC403J
SW7
KSC403J
R62
10K
R62
10K
C66
0.1uF
C66
0.1uF
Figure 4-3 · Flash*Freeze Mode Control
A c tel I G LOO PLU S
FP G A
Flash * Freeze
Mo d e C ontrol
Flash * Freeze Pin
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