XMC-6260-CC
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 14 -
http://www.acromag.com
- 14 -
www.acromag.com
PCIE INTERFACE LOGIC
Dual XAUI Interface
DDR3
Clock Generation
Serial EEPROM
The XMC-6260-CC host interface is through PCI Express 2.0 which provides a
5Gbps interface to the carrier/CPU board. The PCIe interface supports 8
physical functions (PF). SR-IOV is supported on 4 PF with 128 virtual
functions (VF). It supports x1, x2, x4 and x8 link widths. Maximum payload
sizes and memory read request sizes of 128B to 2KB are supported, with up
to 128 outstanding PCIe reads.
The board contains two XAUI ports routed from the T4 ASIC’s integrated full-
duplex Ethernet MACs directly to the P16 XMC connector. Each XAUI port is
comprised of 4 lanes, each operating at a speed of 3.125Gbps. With 8b/10b
encoding, each XAUI port provides 10Gbps throughput in each direction.
These XAUI links correlate with links 2 and 3 of the VITA 42.6 specification.
There is a 64 Meg x 72-bit of DDR3 memory onboard for the purpose of
storing connection states and buffers for up to 32K offloaded connections.
Five DDR3 memory devices are used to form a 72-bit data bus. Each of the
devices are 64 Meg x 16 bit (1Gb) in size.
There is one onboard 50MHz XTAL providing the core clock to the T4 ASIC.
This XTAL is all that is needed in order for the ASIC to internally produce the
necessary clocks needed for operation.
There is a 256Kb Atmel SPI Serial EEPROM which contains all the hardware
configuration including things like pll multipliers and PCIe information. It
also contains information on how to configure the firmware for the T4 ASIC
including things like how to set up the DDR3 and the number of ports
available on the card.
