SERIES IOS-521 I/O SERVER MODULE EIA/TIA-422B SERIAL COMMUNICATION MODULE
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signal. The four modem control inputs (CTS, DSR, DCD, and RI)
are disconnected from their receiver input paths. In addition, the
four modem control outputs (DTR, RTS, OUT1, and OUT2) do
not have transmitter output paths.
Bit-
3 of this register must be set to a logic “1” to enable
the corresponding port to issue an interrupt.
Modem Control Register
MCR Bit
FUNCTION
PROGRAMMING
0
Data Terminal
Ready Output
Signal (DTR)
0= DTR* Not Asserted (Inactive)
1= DTR* Asserted (Active)
A DTR signal path is NOT
SUPPORTED by this model.
Instead, this output is used to
enable the receiver of the port
RxD.
1
Ready to Send
Output Signal
(RTS)
0 = RTS* Not Asserted (Inactive)
1 = RTS* Asserted (Active)
A RTS signal path is NOT
SUPPORTED by this model.
Instead, the output is used to
enable the transmitter of the port
TxD.
2
Not Used
No Effect on External Operation
3
Port Interrupt
Disable/Enable
0 = Interrupt Disabled for this
port.
1 = Interrupt Enabled for this
port.
4
Loop-back
1
0 = Loop-back Disabled
1 = Loop-back Enabled
5
2
Xon Control
0 = Disable Xon
1 = Enable any Xon function. In
this mode any RX character
received will enable Xon.
6
2
Not Used
Must be logic 0
7
2
Divide by Four
0 = Divide by one. The crystal
frequency is unchanged.
1 = Divide by four. After the
crystal frequency is divided by 16
it is further divided by 4 (see
Table 3.2).
Notes (Modem Control Register):
1. MCR Bit 4 provides a local loopback feature for diagnostic
testing of the UART channel. When set high, the UART
serial output (connected to the TXD driver) is set to the
marking (logic 1 state), and the UART receiver serial data
input is disconnected from the RxD receiver path. The
output of the UART transmitter shift register is then looped
back into the receiver shift register input. The control output
(RTS) is internally connected to the control input DSR (while
its associated pin is forced to its high/inactive state). Thus,
in the loopback diagnostic mode, transmitted data is
immediately received, permitting the host processor to verify
the transmit and receive data paths of the selected serial
channel. In this mode, interrupts are generated by
controlling the state of the four lower order MCR bits
internally, instead of by the external hardware paths.
However, no interrupt requests or interrupt vectors are
actually served in loopback mode, and interrupt pending
status is only reflected internally.
2. Bits 5-7 are only programmable when the EFR bit 4 is set to
“1”. The programmed values for these bits are latched when
EFR bit 4 is cleared, preventing existing software from
inadvertently overwriting the extended functions. However,
these MCR bits can not be set if the LCR is set to BF hex.
A power-up or system reset sets all MCR bits to 0.
