SERIES IOS-521 I/O SERVER MODULE EIA/TIA-422B SERIAL COMMUNICATION MODULE
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SIGNALS (INTERNAL & EXTERNAL):
TxD
Reset
High
Interrupt
(RCVR errors)
Read LSR/
Reset
Low
Interrupt
(RCVR data
ready)
Read RCVR
Buffer
Register/
Reset
Low
Interrupt
(THRE)
Read
ISR/Write
THR/Reset
Low
Interrupt
(Modem
Status
Changes)
Read MSR/
Reset
Low
RTS*
Reset
High
IOS-521 PROGRAMMING CONSIDERATIONS
Each serial channel of this module is programmed by the
control registers: LCR, IER, DLL, DLM, MCR, and FCR. These
control words define the character length, number of stop bits,
parity, baud rate, and modem interface. The control registers can
be written in any order, but the IER register should be written last
since it controls the interrupt enables. The contents of these
registers can be updated any time the serial channel is not
transmitting or receiving data.
The complete status of each channel can be read by the host
CPU at any time during operation. Two registers are used to
report the status of a particular channel: the Line Status Register
(LSR) and the Modem Status Register (MSR).
Serial channel data is read from the Receiver Buffer Register
(RBR), and written to the Transmitter Holding Register (THR).
Writing data to the THR initiates the parallel-to-serial transmitter
shift register to the TxD line. Likewise, input data is shifted from
the RxD pin to the Receiver Buffer Register as it is received.
The Scratch Pad Register is used to store the interrupt vector
for the port. In response to an interrupt select cycle, the IOS
module will provide a read of this port. As such, each port may
have a unique interrupt vector assigned. Interrupts are served in
a shifting-priority fashion as a function of the last interrupting port
serviced to prevent continuous interrupts from a higher-priority
interrupt channel from freezing out service of a lower priority
channel.
This board operates in two different modes. In one mode,
this device remains software compatible with the industry
standard 16C450 family of UART‟s, and provides double-
buffering of data registers. In the FIFO Mode (enabled via bit 0 of
the FCR register), data registers are FIFO-buffered so that read
and write operations can be performed while the UART is
performing serial-to-parallel and parallel-to-serial conversions.
Two FIFO modes of operation are possible: FIFO Interrupt
Mode and FIFO Polled Mode. In FIFO Interrupt Mode, data
transfer is initiated by reaching a pre-determined trigger-level or
generating time-out conditions. In FIFO-Polled Mode, there is no
time-out condition indicated or trigger-level reached. The
transmit and the receive FIFO‟s simply hold characters and the
Line Status Register must be read to determine the channel
status.
FIFO Polled-Mode
Resetting all Interrupt Enable Register (IER) bits to 0, with
FIFO Control Register (FCR) Bit 0 =1, puts the channel into the
polled-mode of operation. The receiver and transmitter are
controlled separately and either one or both may be in the polled
mode. In FIFO-Polled Mode, there is no time-out condition
indicated or trigger-level reached, the transmit and the receive
FIFO‟s simply hold characters and the Line Status Register must
be read to determine the channel status.
FIFO-Interrupt Mode
In FIFO Interrupt Mode, data transfer is initiated by reaching
a pre-determined trigger-level or generating a time-out condition.
Please note the following with respect to this mode of operation.
When the receiver FIFO and receiver interrupts are enabled,
the following receiver status conditions apply:
1. LSR Bit 0 is set to 1 when a character is transferred from the
shift register to the receiver FIFO. It is reset to 0 when the
FIFO is empty.
2. The receiver line-status interrupt (ISR=06) has a higher
priority than the received data-available interrupt (ISR=04).
3. The receive data-available interrupt is issued to the CPU
when the programmed trigger level is reached by the FIFO. It
is cleared when the FIFO drops below its programmed trigger
level. The receive data-available interrupt indication
(ISR=04) also occurs when the FIFO reaches its trigger level,
and is cleared when the FIFO drops below its trigger level.
When the receiver FIFO and receiver interrupts are enabled,
the following receiver FIFO character time-out status conditions
apply:
1. A FIFO character time-out interrupt occurs if:
A minimum of one character is in the FIFO.
The last received serial character is longer than four
continuous prior character times ago (if 2 stop bits are
programmed, the second one is included in the time
delay).
The last CPU read of the FIFO is more than four
continuous character times earlier. At 300 baud, and
with 12-bit characters (including start, stop, and parity
bits), the FIFO time-out interrupt causes a latency of
160ms maximum from received character to interrupt
issued.
2. From the clock signal input, the character times can be
calculated. The delay is proportional to the baud rate.
3. The time-out timer is reset after the CPU reads the receiver
FIFO or after a new character is received when there has
been no time-out interrupt.
4. A time-out interrupt is cleared and the timer is reset when the
CPU reads a character from the receiver FIFO.
When the transmit FIFO and transmit interrupts are enabled
(FCR Bit 0 = 1 and IER=01), a transmitter interrupt will occur as
follows:
1. When the transmitter FIFO is empty, the transmitter holding
register interrupt (ISR=02) occurs. The interrupt is cleared
when the Transmitter Holding Register (THR) is written to or
