SERIES IOS-521 I/O SERVER MODULE EIA/TIA-422B SERIAL COMMUNICATION MODULE
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- 7 -
following the start bit. As such, if the data on RxD is a
symmetrical square wave, the center of each successive data cell
will occur within 3.125% of the actual center (this is 50% 16,
providing an error margin of 46.875%). Thus, the start bit can
begin as much as one 16x clock cycle prior to being detected.
IER - Interrupt Enable Register, Ports A-H (R/W)
The Interrupt Enable Register is used to independently
enable/ disable the serial port interrupt sources. Each of the
eight ports have seven unique interrupt sources which are all
mapped to INTREQ0* of the IOS module.
Interrupts are disabled by resetting the corresponding IER bit
low (0), and enabled by setting the IER bit high (1). Disabling the
interrupt system (IER bits 7-5 and 3-0 low) also inhibits the
Interrupt Status Register (ISR) and the interrupt request line
(INTREQ0*).
In addition to enabling the desired bits in the
IER, bit-3 of the Modem Control Register (MCR) must be set
to a logic “1” to enable interrupts.
Interrupt Enable Register
IER BIT
INTERRUPT ACTION
0
0 = Disable Interrupt 1 = Enable Interrupt
This interrupt will be issued when the FIFO has
reached the programmed trigger level or is cleared
when the FIFO drops below the trigger level in the
FIFO mode of operation. Note that the receive FIFO
must also be enabled via bit-0 of the FCR for a
receive interrupt to be issued.
1
0 = Disable Interrupt 1 = Enable Interrupt
This interrupt will be issued whenever the THR is
empty and is associated with bit-1 in the LSR.
2
0 = Disable Interrupt 1 = Enable Interrupt
This interrupt will be issued whenever a fully
assembled receive character is available.
3
0 = Disable Interrupt 1 = Enable Interrupt
Modem Status Interrupt. Since the modem input
signals are not used on this module, this interrupt
should always be disabled.
4
1
0 = Disable Sleep Mode 1 = Enable Sleep Mode
The clock/oscillator circuit is disabled in sleep mode.
The UART will not lose the programmed bits when
sleep mode is activated or deactivated. The UART
will not enter sleep mode if any interrupts are
pending.
5
1
0 = Disable the Receive Xoff Interrupt
1 = Enable the Receive Xoff Interrupt
When software flow control in enabled, and one or
two sequential receive data characters match the
preprogrammed Xoff 1-2 values an interrupt will be
issued.
6
1
0 = Disable RTS Interrupt
1 = Enable RTS Interrupt.
This Interrupt is generated when the RTS pin
transitions from a logic 0 to a logic 1. RTS is not
output by this module. Instead RTS is used to
enable the transmitter of the port. This interrupt
should always be disabled.
7
1
0 = Disable CTS Interrupt
1 = Enable CTS Interrupt.
This interrupt will be issued when the CTS pin
transitions from a logic 0 to a logic 1. Since CTS is
not used on this module, this interrupt should always
IER BIT
INTERRUPT ACTION
be disabled.
Notes (Interrupt Enable Register):
1.
Bits 4 to 7 are only programmable when the EFR bit 4 is
set to “1”.
A power-up or system reset sets all IER bits to 0 (bits 7-0
forced low).
ISR - Interrupt Status Register, Ports A-H (READ Only)
The Interrupt Status Register is used to indicate that a
prioritized interrupt is pending and the type of interrupt that is
pending. Six levels of prioritized interrupts are provided to
minimize software interaction. Performing a read cycle on the
ISR will provide the user with the highest pending interrupt level
to be serviced. No other interrupts are acknowledged until the
pending interrupt is serviced. Whenever the interrupt status
register is read, the interrupt status is cleared. Note, only the
current pending interrupt is cleared by the read. A lower level
interrupt may be seen after re-reading the interrupt status bits.
The eight individual ports share the IOS module INTREQ0*
signal. Each port has an opportunity to issue an interrupt in a
round robin fashion. That is, interrupt vectors are served
according to a shifting priority scheme that is a function of the last
interrupting port served.
The following interrupt source table shows the data values
(bit 0-5) for the six prioritized interrupt levels and the interrupt
sources associated with each of these interrupt levels.
PRIORITY
LEVEL
ISR BITS
Bit5 to Bit0
Source of the Interrupt
1
000110
Receiver Line Status (see LSR
bits 1-4)
2
000100
Received Data Ready or Trigger
Level reached.
2
001100
Receive Data Time Out.
3
000010
Transmitter Holding Register
Empty
4
000000
MSR (Modem Status Register)
5
010000
Received Xoff signal special
character
6
100000
CTS, RTS change of state
Note that ISR bit 0 can be used to indicate whether an
interrupt is pending (bit 0 low when interrupt is pending). ISR bits
1 & 2 are used to indicate the highest priority interrupt pending.
ISR bit 3 is always logic 0 in the 16C450 mode. ISR bit 3 is set
along with bit 2 when in the FIFO mode and a timeout interrupt is
pending. Bit 4 set indicates a Xoff/special character detected
interrupt pending. Bit 5 indicates a pending interrupt due to a
change of state on the CTS or RTS signals.
Bits 6 and 7 are set when bit 0 of the FIFO Control Register
is set to 1. A power-
up or system reset sets ISR bit 0 to logic “1”,
and bits 1 to 7 to logic “0”.
