SERIES IOS-521 I/O SERVER MODULE EIA/TIA-422B SERIAL COMMUNICATION MODULE
__________________________________________________________________________________________
- 10 -
LSR - Line Status Register, Ports A-H (Read/Write-Restricted)
The Line Status Register (LSR) provides status indication
corresponding to the data transfer. LSR bits 1-4 are the error
conditions that produce receiver line-status interrupts (a priority 1
interrupt in the Interrupt Identification Register). The line status
register may be written, but this is intended for factory test and
should be considered read-only by the application software.
Line Status Register
LSR Bit
FUNCTION
PROGRAMMING
0
Data Ready
(DR)
0 = Not Ready (reset low by CPU
Read of RBR or FIFO)
1 = Data Ready (set high when
character received and transferred
into the RBR or FIFO).
1
Overrun
Error (OE)
0 = No Error
1 = Indicates that data in the RBR is
not being read before the next
character is transferred into the RBR,
overwriting the previous character. In
the FIFO mode, it is set after the
FIFO is filled and the next character
is received. The overrun error is
detected by the CPU on the first LSR
read after it happens. The character
in the shift register is not transferred
into the FIFO, but is overwritten.
This bit is reset low when the CPU
reads the LSR.
2
Parity Error
(PE)
0 = No Error
1 = Parity Error - the received
character does not have the correct
parity as configured via LCR bits 3 &
4. This bit is set high on detection of
a parity error and reset low when the
host CPU reads the contents of the
LSR. In the FIFO mode, the parity
error is associated with a particular
character in the FIFO (LSR Bit 2
reflects the error when the character
is at the top of the FIFO).
3
Framing
Error (FE)
0 = No Error
1 = Framing Error - Indicates that the
received character does not have a
valid stop bit (stop bit following last
data bit or parity bit detected as a
zero/space bit). This bit is reset low
when the CPU reads the contents of
the LSR. In FIFO mode, the framing
error is associated with a particular
character in the FIFO (LSR Bit 3
reflects the error when the character
is at the top of the FIFO).
Line Status Register...continued
LSR Bit
FUNCTION
PROGRAMMING
4
Break
Interrupt
(BI)
0 = No Break
1 = Break the received data input has
been held in the space (logic 0) state
for more then a full-word
transmission time (start bits+ data+
parity bit+ stop bits). Reset upon
read of LSR. In FIFO mode, this bit
is associated with a particular
character in the FIFO and reflects the
Break Interrupt when the break
character is at the top of the FIFO. It
is detected by the host CPU during
the first LSR read. Only one “0”
character is loaded into the FIFO
when BI occurs.
5
Transmitter
Holding
Register
Empty
(THRE)
0 = Not Empty
1 = Empty - indicates that the
channel is ready to accept a new
character for transmission. Set high
when character is transferred from
the THR into the transmitter shift
register. Reset low by loading the
THR (It is not reset by a host CPU
read of the LSR). In FIFO mode, this
bit is set when the Tx FIFO is empty
and cleared when one byte is written
to the Tx FIFO. When a Transmitter
Holding Register Empty interrupt is
enabled by IER bit 1, this signal
causes a priority 3 interrupt in the
ISR. If the ISR indicates that this
signal is causing the interrupt, the
interrupt is cleared by a read of the
ISR.
6
Transmitter
Empty
(TEMT)
0 = Not Empty
1 = Transmitter Empty - set when
both the Transmitter Holding Register
(THR) and the Transmitter Shift
Register (TSR) are both empty.
Reset low when a character is loaded
into the THR and remains low until
the character is transmitted (it is not
reset low by a read of the LSR). In
FIFO mode, this bit is set when both
the transmitter FIFO and shift register
are empty.
7
Receiver
FIFO Error
0 = No Error in FIFO (it is always 0
in 16C450 mode--FCR bit 0 low).
1 = Error in FIFO - set when one of
the following data errors is present in
the FIFO: parity error, framing error,
or break interrupt indication. Cleared
by a host CPU read of the LSR if
there are no subsequent errors in the
FIFO. FIFO read of offending
character is also required.
Note that LSR Bits 1-4 (OE, PE, FE, BI) are the error
conditions that produce a receiver-line-status interrupt (a priority 1
interrupt in the ISR register when any one of these conditions are
detected). This interrupt is enabled by setting IER bit 2 to “1”.
A power-up or system reset sets all LSR bits to 0, except bits
5 and 6 which are high.
