Acromag IOS-440, User Manual

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SERIES IOS-440 I/O SERVER MODULE 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com
Table 3.1B: IOS-440 R/W Space Address (Hex) Memory Map
HIGH
Base
Addr+
MSB
D15 D08
LSB
D07 D00
LOW
Base
Addr+
INDEPENDENT FIXED FUNCTION REGISTERS:
11
1D
Not Driven
1
NOT USED
2
10
1C
1F
Not Driven
1
READ/WRITE
Interrupt Enable Register
(Bit 0=1 enables
INTREQ0)
& Software Reset
Generator (Bit 1=1
Generates Reset)
1E
21
2D
Not Driven
1
NOT USED
2
20
2C
2F
Not Driven
1
READ/WRITE
Interrupt Vector Register
2E
31
7F
Not Driven
1
NOT USED
2
30
7E
Notes (Table 3.1B):
1. The upper 8 bits of these registers are not driven and pull-ups
on the carrier data bus will cause these bits to read high (1‟s).
2. The IOS will re
spond to addresses that are “Not Used” with
an active IOS module acknowledge (ACK*). The board will
return “0” for all address reads that are not used or reserved.
3. All Reads and Writes are 0 wait state.
4. Writes to these registers may have an adverse effect on
module operation. Use the Port 7 Write Mask to prevent
writing to these registers.
REGISTER DEFINITIONS
STANDARD MODE REGISTERS
Port Registers
(Standard Mode, Ports 0-3, Read Only)
Four registers are provided to monitor 32 possible input
points. Data is read from one of four groups of eight input lines
(Ports 0-3), as designated by the address and read and write
signals. Each port assigns the least significant data line (D0) to
the least significant input line of the port grouping (e.g. IN00 for
port 0 to D0). A read of this register returns the status (ON/OFF)
of the input point.
Do not write to these registers. The Mask
Register is used to disable writes to these ports. On power-up or
reset, the ports are reset to 0.
Write Mask Register & Enhanced Mode Select Register
(Standard Mode, Port 7, Read/Write)
This register is used to mask the ability to write data to the
four I/O ports of this model. Writing a „1‟ to bits 0-3 of the Mask
Register will mask ports 0-3 respectively, from inadvertent writes.
A read of this register will return the status of the mask in bits 0-3.
Standard Mode Write Mask Register (Port 7)
BIT WRITE TO REGISTER READ FROM REGISTER
0 Port 0 Write Mask Port 0 Write Mask
1 Port 1 Write Mask Port 1 Write Mask
2 Port 2 Write Mask Port 2 Write Mask
3 Port 3 Write Mask Port 3 Write Mask
4-7 NOT USED NOT USED
Bits 4-7 of this register are not used. On power-up reset, all
bits are set to „0‟.
To switch to Enhanced Mode, four unique bytes must be
written to port 7, in consecutive order, without doing any reads or
writes to any other port and with interrupts disabled. The data
pattern to be written is 07H, 0DH, 06H, and 12H, in order, and
this must be written immediately after reset or power-up.
ENHANCED MODE
BANK 0 REGISTERS
Port Registers
(Enhanced Mode Bank 0, Ports 0-3, Read Only)
Four input registers are provided to monitor 32 possible input
points. Data is read from one of four groups (Ports 0-3) of eight
input lines, as designated by the address. Each port assigns the
least significant data line (D0) to the least significant input line of
the port grouping (e.g. IN00 of port 0 to D0). A read of this
register returns the status (ON/OFF) of the input signal.
Do not
write to these registers. The Mask Register is used to disable
writes to these ports.
Write Mask Register and Bank Select Register 0
(Enhanced Mode Bank 0, Port 7, Read/Write)
This register is used to mask the ability to write data to the
four I/O ports of this model. Writing a „1‟ to bits 0-3 of the Mask
Register will mask ports 0-3 respectively, from inadvertent writes.
A read of this register will return the status of the mask in bits 0-3.
Enhanced Mode Write Mask Register (Port 7)
BIT WRITE TO REGISTER READ FROM REGISTER
0 Port 0 Write Mask Port 0 Write Mask
1 Port 1 Write Mask Port 1 Write Mask
2 Port 2 Write Mask Port 2 Write Mask
3 Port 3 Write Mask Port 3 Write Mask
4-5 NOT USED NOT USED
6 Bank Select Bit 0 Bank Status Bit 0
7 Bank Select Bit 1 Bank Status Bit 1
Bits 6 & 7 of this register are used to select/monitor the bank
of registers to be addressed. In Enhanced Mode, three banks
(banks 0-2) of eight registers may be addressed. Bank 0
registers are similar to the Standard Mode bank of registers.
Bank 1 allows the 32 event inputs to be monitored and controlled.
Bank 2 registers control the debounce circuitry of the event
inputs. Bits 7 and 6 select the bank as follows: