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SERIES IOS-440 I/O SERVER MODULE                                32-CHANNEL ISOLATED DIGITAL INPUT MODULE 
_________________________________________________________________________________________

 

- 5 - 

Acromag, Inc.  Tel:248-295-0310  Fax:248-624-9234  Email:[email protected]  http://www.acromag.com 

 

Table 3.1A:  IOS-440 R/W Space Address (Hex) Memory Map 

HIGH 
Base 
Addr+ 

 

MSB 

D15      D08 

 

LSB 

D07                   D00 

LOW 
Base 
Addr+ 

STANDARD MODE (DEFAULT) REGISTER DEFINITIONS: 

01 

 

 

Not Driven

4

 

READ

1

 - Port 0 

Register IN00-IN07 

 
00 

03 

 

Not Driven

4

 

READ

1

 - Port 1 

Register IN08-IN/15 

 
02 

05 

 

Not Driven

4

 

READ

1

 - Port 2 

Register IN16-IN23 

 
04 

07 

 

Not Driven

4

 

READ

1

 - Port 3 

Register IN24-IN31 

 
06 

09 

 

Not Driven

4

 

READ/WRITE - Port 4 

NOT USED

2

 

 
08 

0B 

 

Not Driven

4

 

READ/WRITE - Port 5 

NOT USED

2

 

 
0A 

0D 

 

Not Driven

4

 

READ/WRITE - Port 6 

NOT USED

 
0C 

0F 

 

Not Driven

4

 

READ/WRITE - Port 7 

WRITE MASK REGISTER 

AND ENHANCED MODE 

SELECT REGISTER

3

 

 
 
 
0E 

11 

 

7F 

 

NOT USED

2

 

 

10 

 

7E 

 

Notes (Table 3.1A): 

1.   Writes to these registers may have an adverse effect on 

module operation. Use the Port 7 Write Mask to prevent 
writing to these registers. 

2.   The IOS will respond to addresses that are “Not Used” with 

an active IOS module acknowledge (ACK*).  The board will 
return “0” for all address reads that are not used or reserved.

  

 

3.   Writing four unique bytes (07H, 0DH, 06H, and 12H) to port 7, 

in consecutive order, will switch to Enhanced Mode.  Perform 
this operation after reset or power-up with interrupts disabled.  
Do not read or write to any other port between writes. 

4.   The upper 8 bits of these registers are not driven and pull-ups 

on the carrier data bus will cause these bits to read high (1‟s). 

 

Table 3.1B:  IOS-440 R/W Space Address (Hex) Memory Map 

HIGH 
Base 
Addr+ 

 

MSB 

D15      D08 

 

LSB 

D07                   D00 

LOW 
Base 
Addr+ 

ENHANCED MODE, REGISTER BANK [0] DEFINITIONS: 

01 

 

 

Not Driven

1

 

READ

4

 - Port 0 

Register IN00-IN07 

 
00 

03 

 

Not Driven

1

 

READ

4

 -Port 1 

Register IN08-IN15 

 
02 

05 

 

Not Driven

1

 

READ

4

 - Port 2 

Register IN16-IN23 

 
04 

07 

 

Not Driven

1

 

READ

4

 - Port 3 

Register IN24-IN31 

 
06 

09 

 

Not Driven

1

 

READ

2

 - Port 4 

NOT USED 

 
08 

0B 

 

Not Driven

1

 

READ

2

 - Port 5 

NOT USED 

 
0A 

0D 

 

Not Driven

1

 

READ

2

 - Port 6 

NOT USED 

 
0C 

0F 

 

Not Driven

1

 

READ - Port 7 

READ MASK REGISTER 

(Also Current Bank Status) 

 
 
0E 

0F 

 

Not Driven

1

 

WRITE - Port 7 

WRITE MASK REGISTER 

(Also Bank Select 

Register) 

 
 
0E 

 

Table 3.1B:  IOS-440 R/W Space Address (Hex) Memory Map 

HIGH 
Base 
Addr+ 

 

MSB 

D15      D08 

 

LSB 

D07                   D00 

LOW 
Base 
Addr+ 

ENHANCED MODE, REGISTER BANK [1] DEFINITIONS: 

01 

 

 

Not Driven

1

 

READ - Port 0 

Event Sense Status Reg. 

(Port 0 Input points 0-7) 

 
 
00 

01 

 

 

Not Driven

1

 

WRITE - Port 0 

Event Sense Clear Reg 
(Port 0 Input points 0-7) 

 
 
00 

03 

 

Not Driven

1

 

READ - Port 1 

Event Sense Status Reg.  

(Port 1 Input points 8-15) 

 
 
02 

03 

 

Not Driven

1

 

WRITE - Port 1 

Event Sense Clear Reg 

(Port 1 Input points 8-15) 

 
 
02 

05 

 

Not Driven

1

 

READ - Port 2 

Event Sense Status Reg. 

(Port 2 Input points 16-23) 

 
 
04 

05 

 

Not Driven

1

 

WRITE - Port 2 

Event Sense Clear Reg 

(Port 2 Input points 16-23) 

 
 
04 

07 

 

Not Driven

1

 

READ - Port 3 

Event Sense Status Reg. 

(Port 3 Input points 24-31) 

 
 
06 

07 

 

Not Driven

1

 

WRITE - Port 3 

Event Sense Clear Reg 

(Port 3 Input points 24-31) 

 
 
06 

09 

 

Not Driven

1

 

READ - Port 4 

NOT USED

 
08 

09 

 

Not Driven

1

 

WRITE - Port 4 

NOT USED

2

 

 
08 

0B 

 

Not Driven

1

 

READ - Port 5 

NOT USED

2

 

 
0A 

0B 

 

Not Driven

1

 

WRITE - Port 5 

NOT USED

2

 

 
0A 

0D 

 

Not Driven

1

 

READ - Port 6 

Event Status for Ports 0-3 

and Interrupt Status Reg. 

 
 
0C 

0D 

 

Not Driven

1

 

WRITE - Port 6 

Event Polarity Control 

Register for Port 0-3 

 
 
0C 

0F 

 

Not Driven

1

 

READ - Port 7 

Current Bank Status Reg. 

 
0E 

0F 

 

Not Driven

1

 

WRITE - Port 7 

Bank Select Register 

 
0E 

ENHANCED MODE, REGISTER BANK [2] DEFINITIONS: 

01 

 

 

Not Driven

1

 

READ/WRITE - Port 0 

Debounce Control Register 

(for Ports 0-3) 

 
 
00 

03 

 

Not Driven

1

 

READ/WRITE - Port 1 

Debounce Duration Reg. 0 

(for Ports 0-3) 

 
 
02 

05 

 

Not Driven

1

 

 

NOT USED 

 
 
04 

07 

 

Not Driven

1

 

WRITE ONLY - Port 3 

Debounce Clock Select 

 
06 

09 

 

0D 

 

Not Driven

1

 

Port 4,5,6 

NOT USED

2

 

 

08 

 

0C 

0F 

 

Not Driven

1

 

READ/WRITE - Port 7 

Bank Status/Select 

Register 

 
 
0E 

Summary of Contents for IOS-440

Page 1: ...ANUAL ACROMAG INCORPORATED Tel 248 295 0310 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A solutions acromag com Copyright 2009 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 839 B11C007 retired ...

Page 2: ...C The inputs normally function as independent input level detectors without interrupts However each input line includes built in event sense circuitry with programmable polarity debounce and interrupt support Inputs also include hysteresis for increased noise immunity The IOS 440 utilizes state of the art Surface Mounted Technology SMT to achieve its wide functionality and is an ideal choice for a...

Page 3: ...ed keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected wi...

Page 4: ...ual inputs also include selectable hardware debounce in Enhanced Mode For event sensing the Enhanced Mode allows a specific input level transition High to Low Low to High or Change of State to be detected and optionally generate an interrupt Memory is organized and addressed in separate banks of eight registers or ports eight ports to a bank The Standard Mode of operation addresses the first group...

Page 5: ... Register IN08 IN15 02 05 Not Driven1 READ4 Port 2 Register IN16 IN23 04 07 Not Driven1 READ4 Port 3 Register IN24 IN31 06 09 Not Driven1 READ2 Port 4 NOT USED 08 0B Not Driven1 READ2 Port 5 NOT USED 0A 0D Not Driven1 READ2 Port 6 NOT USED 0C 0F Not Driven1 READ Port 7 READ MASK REGISTER Also Current Bank Status 0E 0F Not Driven1 WRITE Port 7 WRITE MASK REGISTER Also Bank Select Register 0E Table ...

Page 6: ... return the status of the mask in bits 0 3 Standard Mode Write Mask Register Port 7 BIT WRITE TO REGISTER READ FROM REGISTER 0 Port 0 Write Mask Port 0 Write Mask 1 Port 1 Write Mask Port 1 Write Mask 2 Port 2 Write Mask Port 2 Write Mask 3 Port 3 Write Mask Port 3 Write Mask 4 7 NOT USED NOT USED Bits 4 7 of this register are not used On power up reset all bits are set to 0 To switch to Enhanced ...

Page 7: ... the carrier board see Interrupt Enable Register Event Interrupt Status Register for Ports 0 3 BIT READ EVENT STATUS REGISTER 0 Port 0 Interrupt Status IN00 IN07 1 Port 1 Interrupt Status IN08 IN15 2 Port 2 Interrupt Status IN16 IN23 3 Port 3 Interrupt Status IN24 IN31 4 6 NOT USED 7 Interrupt Status Flag Event Polarity Control Register For Ports 0 3 Enhanced Mode Bank 1 Port 6 Write Only A write ...

Page 8: ...OS clock for debounce The IOS 440 always uses the 8MHz clock for debounce and this register is only provided to facilitate backwards compatibility with the IOS 440 This register is cleared following a reset Bank Select Write Status Read Register 2 Enhanced Mode Bank 2 Port 7 Read and Write Bits 0 5 of this register are not used Bits 6 7 of this register are used to indicate read or select write th...

Page 9: ... input lines 0 31 Additionally ports are grouped eight to a bank There are four banks of ports used for controlling this module Standard Mode plus Enhanced Mode Banks 0 1 and 2 plus 2 additional registers for enabling the interrupt request line generating a software reset and storing the interrupt vector Each port input line is bipolar and accepts both positive and negative input voltages in two r...

Page 10: ... channel has been reset by writing a 1 to the corresponding event sense bit in the Event Sense Status Register after writing 0 to clear the event sense flip flop Interrupts may be reflected internally and reported by polling the module or optionally reported to the carrier by enabling control of the Interrupt Request line Intreq0 Control of this line is initiated via Bit 0 of the Interrupt Enable ...

Page 11: ...or while writing a 0 clears the event sensed without enabling further event sensing 9 Write 00H to the port 7 address to select register bank 0 where the port 0 input channels may be write masked Note that the port 7 address bank selection only operates from bits 6 7 of this register Likewise this register has a dual function depending on whether a read or write is executed As such the polarity se...

Page 12: ...en a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have b...

Page 13: ...with no digital upsets Conducted RF Immunity CRFI Complies with EN61000 4 6 3V rms 150KHz to 80MHz and European Norm EN50082 1 with no digital upsets Electromagnetic Interference Immunity EMI No digital upset under the influence of EMI from switching solenoids commutator motors and drill motors Electrostatic Discharge Immunity ESD Complies with EN61000 4 2 Level 3 8KV enclosure port air discharge ...

Page 14: ...ebounce times are programmable and derived from the 8MHz system clock in combination with the debounce duration register value Debounce times are applied at the FPGA input and do not include opto coupler delay time Debounce values of 4us 64us 1ms and 8ms may be configured Each debounce time has an error of up to 375ns Interrupts Each channel has configurable interrupts They may be configured for h...

Page 15: ...LE 32 CHANNEL ISOLATED DIGITAL INPUT MODULE _________________________________________________________________________________________ 15 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com ...

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