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SERIES IOS-440 I/O SERVER MODULE                                32-CHANNEL ISOLATED DIGITAL INPUT MODULE 
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Acromag, Inc.  Tel:248-295-0310  Fax:248-624-9234  Email:[email protected]  http://www.acromag.com 

 

board unless control of the Interrupt Request Line 0 (IntReq0) 
has been enabled via the Interrupt Enable Register (IER). 
 

IOS Identification PROM - (Read Only, 32 Even-Byte 
Addresses)

 

 

Each IOS module contains an identification (ID) PROM that 

resides in the IOS ID space..  This area of memory contains 32 
bytes of information at most.  Both fixed and variable information 
may be present within the ID PROM.  Fixed information includes 
the "IOS" identifier, model number, and manufacturer's 
identification codes.  Variable information includes unique 
information required for the module.  The IOS-440 ID PROM 
does not contain any variable (e.g. unique calibration) 
information.  ID PROM bytes are addressed using only the even 
addresses in a 64 byte block.  The IOS-440 ID PROM contents 
are shown in Table 3.2.  Note that the base-address for the IOS 
module ID space (see your carrier board instructions) must be 
added to the addresses shown to properly access the ID PROM. 
 

Table 3.2: IOS-440 ID Space Identification (ID) PROM  

Hex Offset 

From ID 

PROM Base 

Address 

 

Numeric 

 Value 

 (Hex) 

 
 
 

Field Description 

00 

49 

 

02 

50 

 

04 

41 

 

06 

43 

 

08 

A3 

Acromag ID Code 

0A 

10 

IOS Model Code

1

  

0C 

00 

Not Used (Rev) 

0E 

00 

Reserved 

10 

00 

Not Used  

12 

00 

Not Used  

14 

0C 

Total Number of 

ID PROM Bytes 

16 

3B 

CRC 

18 to 3E 

00 

Not Used 

 
Notes (Table 3.2):

 

1.   The IOS model number is represented by a two-digit code 

within the ID PROM (IOS440 model is represented by 10 
Hex). 

2.   Execution of an ID PROM read requires 0 wait states. 

 
THE EFFECT OF RESET 
 

A power-up or bus-initiated software reset will place the 

module in the Standard Operating Mode (input only, no event 
sensing, no interrupts, and no debounce).  Further, all event 
inputs are reset, set to positive events, and disabled following 
reset.  A false input signal is ensured for inputs left floating (i.e. 
reads as 0).  The Interrupt Enable Register (IER) and Interrupt 
Vector Register (IVR) are also cleared (except for IER generated 
software resets). 

 
Another form of software reset (IER register initiated) acts 

similar to a carrier or power-up reset, except that it is not driven 
by the carrier.  For the software reset, the Interrupt Vector 
Register and Interrupt Enable Register are not cleared.  Reset in 
this manner has been provided for use when the interrupt vector 
and interrupt enable information must be preserved. 

 
 

Basic Input Operation 

 

Note that the input lines of this module are assembled in 

groups of eight.  Each group of eight lines is referred to as a port.  
Ports 0-3 control and monitor input lines 0-31.  Additionally, ports 
are grouped eight to a bank.  There are four banks of ports used 
for controlling this module (Standard Mode, plus Enhanced Mode 
Banks 0, 1, and 2), plus 2 additional registers for enabling the 
interrupt request line, generating a software reset, and storing the 
interrupt vector. 
 

Each port input line is bipolar and accepts both positive and 

negative input voltages in two ranges according to the model 
number.  Individual input lines of a port share a common signal 
connection with each other.  Separate commons are provided for 
each port to facilitate port-to-port isolation.  A high signal is 
derived from the absolute value of the input voltage measured 
between the input line and the port common for the input range of 
16-40V for the IOS-440-2 model.  Inputs are non-inverting and 
inputs left floating (not recommended) will register a low (false=0) 
input indication. 
 

In both the Standard and Enhanced operating modes, each 

group of eight parallel input lines (a port) are isolated and gated 
to the dat

a bus D0..D7 lines.  A high input will read as “1” and all 

inputs include hysteresis and programmable debounce.   
 

Enhanced Operating Mode 
 

In the Enhanced Mode of operation, each port input may act 

as an event sensor and generate interrupts.  Likewise, 
programmable debounce logic is also available.  Event sensing is 
used to selectively sense high-to-low level, or low-to-high level 
transitions on the input lines at the range thresholds of  6V (“-2” 
unit).  Event polarities may be defined as positive or negative for 
individual nibbles (groups of 4 input lines, or half ports).  
Interrupts may also be triggered by events.  The optional 
debounce logic can act as a filter to “glitches” or transients 
present on received signals. 

 
The Enhanced Mode is entered by writing four unique bytes 

to the Standard Mode Port 7 register, in consecutive order, 
without doing any reads or writes to any other port and with 
interrupts disabled.  The data pattern to be written is 07H, 0DH, 
06H, and 12H, and this must be written immediately after reset or 
power-up. 

 
In Enhanced Mode, there are three groups (or banks) of eight 

registers or ports.  The first group, bank 0, provides register 
functionality similar to Standard Mode (input level monitoring).  
The second group, bank 1, provides monitor and control of the 
event sense inputs.  The third group, bank 2, is used to configure 
the debounce circuitry for each input while in the Enhanced 
Mode. 

 
Event Sensing 
 

The IOS-440 has edge-programmable event sense logic 

built-in for all 32 input lines, IN00 through IN31.  Event sensing 
may be configured to generate an interrupt to the carrier, or to 
merely reflect the interrupt internally.  Event sensing is enabled in 
Enhanced Mode only and inputs can be set to detect positive or 
negative events, on a nibble-by-nibble (group of 4 input lines) 
basis.  The event sensing is enabled on an individual channel 
basis.  You can combine event sensing with the built-in debounce 

Summary of Contents for IOS-440

Page 1: ...ANUAL ACROMAG INCORPORATED Tel 248 295 0310 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A solutions acromag com Copyright 2009 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 839 B11C007 retired ...

Page 2: ...C The inputs normally function as independent input level detectors without interrupts However each input line includes built in event sense circuitry with programmable polarity debounce and interrupt support Inputs also include hysteresis for increased noise immunity The IOS 440 utilizes state of the art Surface Mounted Technology SMT to achieve its wide functionality and is an ideal choice for a...

Page 3: ...ed keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected wi...

Page 4: ...ual inputs also include selectable hardware debounce in Enhanced Mode For event sensing the Enhanced Mode allows a specific input level transition High to Low Low to High or Change of State to be detected and optionally generate an interrupt Memory is organized and addressed in separate banks of eight registers or ports eight ports to a bank The Standard Mode of operation addresses the first group...

Page 5: ... Register IN08 IN15 02 05 Not Driven1 READ4 Port 2 Register IN16 IN23 04 07 Not Driven1 READ4 Port 3 Register IN24 IN31 06 09 Not Driven1 READ2 Port 4 NOT USED 08 0B Not Driven1 READ2 Port 5 NOT USED 0A 0D Not Driven1 READ2 Port 6 NOT USED 0C 0F Not Driven1 READ Port 7 READ MASK REGISTER Also Current Bank Status 0E 0F Not Driven1 WRITE Port 7 WRITE MASK REGISTER Also Bank Select Register 0E Table ...

Page 6: ... return the status of the mask in bits 0 3 Standard Mode Write Mask Register Port 7 BIT WRITE TO REGISTER READ FROM REGISTER 0 Port 0 Write Mask Port 0 Write Mask 1 Port 1 Write Mask Port 1 Write Mask 2 Port 2 Write Mask Port 2 Write Mask 3 Port 3 Write Mask Port 3 Write Mask 4 7 NOT USED NOT USED Bits 4 7 of this register are not used On power up reset all bits are set to 0 To switch to Enhanced ...

Page 7: ... the carrier board see Interrupt Enable Register Event Interrupt Status Register for Ports 0 3 BIT READ EVENT STATUS REGISTER 0 Port 0 Interrupt Status IN00 IN07 1 Port 1 Interrupt Status IN08 IN15 2 Port 2 Interrupt Status IN16 IN23 3 Port 3 Interrupt Status IN24 IN31 4 6 NOT USED 7 Interrupt Status Flag Event Polarity Control Register For Ports 0 3 Enhanced Mode Bank 1 Port 6 Write Only A write ...

Page 8: ...OS clock for debounce The IOS 440 always uses the 8MHz clock for debounce and this register is only provided to facilitate backwards compatibility with the IOS 440 This register is cleared following a reset Bank Select Write Status Read Register 2 Enhanced Mode Bank 2 Port 7 Read and Write Bits 0 5 of this register are not used Bits 6 7 of this register are used to indicate read or select write th...

Page 9: ... input lines 0 31 Additionally ports are grouped eight to a bank There are four banks of ports used for controlling this module Standard Mode plus Enhanced Mode Banks 0 1 and 2 plus 2 additional registers for enabling the interrupt request line generating a software reset and storing the interrupt vector Each port input line is bipolar and accepts both positive and negative input voltages in two r...

Page 10: ... channel has been reset by writing a 1 to the corresponding event sense bit in the Event Sense Status Register after writing 0 to clear the event sense flip flop Interrupts may be reflected internally and reported by polling the module or optionally reported to the carrier by enabling control of the Interrupt Request line Intreq0 Control of this line is initiated via Bit 0 of the Interrupt Enable ...

Page 11: ...or while writing a 0 clears the event sensed without enabling further event sensing 9 Write 00H to the port 7 address to select register bank 0 where the port 0 input channels may be write masked Note that the port 7 address bank selection only operates from bits 6 7 of this register Likewise this register has a dual function depending on whether a read or write is executed As such the polarity se...

Page 12: ...en a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have b...

Page 13: ...with no digital upsets Conducted RF Immunity CRFI Complies with EN61000 4 6 3V rms 150KHz to 80MHz and European Norm EN50082 1 with no digital upsets Electromagnetic Interference Immunity EMI No digital upset under the influence of EMI from switching solenoids commutator motors and drill motors Electrostatic Discharge Immunity ESD Complies with EN61000 4 2 Level 3 8KV enclosure port air discharge ...

Page 14: ...ebounce times are programmable and derived from the 8MHz system clock in combination with the debounce duration register value Debounce times are applied at the FPGA input and do not include opto coupler delay time Debounce values of 4us 64us 1ms and 8ms may be configured Each debounce time has an error of up to 375ns Interrupts Each channel has configurable interrupts They may be configured for h...

Page 15: ...LE 32 CHANNEL ISOLATED DIGITAL INPUT MODULE _________________________________________________________________________________________ 15 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com ...

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