SERIES IOS-440 I/O SERVER MODULE 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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Bank Select Status Register 1
(Enhanced Mode Bank 1, Port 7, Read Only)
Bits 0-5 of this register are not used. Bits 6 & 7 of this
register are used to indicate the bank of registers to be
addressed. In Enhanced Mode, three banks (banks 0-2) of eight
registers may be addressed. Bank 0 is similar to the Standard
Mode bank of registers. Bank 1 allows the 32 event inputs to be
monitored and controlled. Bank 2 registers control the debounce
circuitry of the event inputs. Bits 7 and 6 of this register select
the bank as follows:
Bank Selected Status Register (Read)
Bit 7 Bit 6
BANK OF REGISTERS
00
Bank 0 - Read Inputs
01
Bank 1 - Event Status/Clear
10
Bank 2 - Event Debounce Control, Clock, &
Duration
11
INVALID - DO NOT WRITE
BANK 2 REGISTERS
Debounce Control Register
(Enhanced Mode Bank 2, Port 0, Read/Write)
This register is used to control whether each individual port is
to be passed through the debounce logic before being recognized
by the circuitry. A “0” disables the debounce logic, and a “1”
enables the debounce logic. Debounce applies to both inputs
and event sense inputs, and only in Enhanced Mode.
Furthermore after enabling the debounce circuitry, wait at
least three times the programmed debounce duration prior to
reading the input ports or event signals to insure valid data.
Debounce Control Register
BIT
DEBOUNCE CONTROL
“0”
“1”
0
Port 0 (IN00-IN07)
Disable
Enable
1
Port 1 (IN08-IN15)
2
Port 2 (IN16-IN23)
3
Port 3 (IN24-IN31)
4-7
NOT USED
Debounce Duration Register 0
(Enhanced Mode Bank 2, Port 1, Read/Write)
This register controls the duration of debounce on each input.
Register 0 controls debounce for ports 0-3. The 8MHz IOS
system clock has the debounce times shown below. Note that
this time applies to the FPGA input and does not include the
opto-coupler time delay.
Debounce Duration Register 0: Duration (8MHz):
BIT
DEBOUNCE CONTROL
Bit
1,0
Time
0
Port 0 Debounce Value Bit 0
00
4us
1
Port 0 Debounce Value Bit 1
01
64us
2
Port 1 Debounce Value Bit 0
10
1ms
3
Port 1 Debounce Value Bit 1
11
8ms
4
Port 2 Debounce Value Bit 0
5
Port 2 Debounce Value Bit 1
6
Port 3 Debounce Value Bit 0
7
Port 3 Debounce Value Bit 1
This register is cleared following a reset.
Debounce Clock Select Register
(Enhanced Mode Bank 2, Port 3, Write Only)
On the original IOS-440, this register was used to select the
8MHz IOS clock for debounce. The IOS-440 always uses the
8MHz clock for debounce and this register is only provided to
facilitate backwards compatibility with the IOS-440. This register
is cleared following a reset.
Bank Select (Write) & Status (Read) Register 2
(Enhanced Mode Bank 2, Port 7, Read and Write)
Bits 0-5 of this register are not used. Bits 6 & 7 of this
register are used to indicate (read) or select (write) the bank of
registers to be addressed. In Enhanced Mode, three banks
(banks 0, 1, & 2) of eight registers may be addressed. Bank 0
registers are similar to the Standard Mode bank of registers.
Bank 1 allows the 32 event inputs to be monitored and controlled.
Bank 2 registers control the debounce circuitry of the event
inputs. Bits 7 and 6 select/indicate the bank as follows:
Bank Select (Write) & Status (Read) Register
Bit 7 Bit 6
BANK OF REGISTERS
00
Bank 0 - Read Input Signals
01
Bank 1 - Event Status/Clear
10
Bank 2 - Event Debounce Control, Clock, &
Duration
11
INVALID - DO NOT WRITE
INDEPENDENT FIXED FUNCTION CONTROL REGISTERS
Interrupt Enable & Software Reset Register
(Read/Write, Base + 1EH)
Bit 0 of this register specifies if the internal event sense
interrupts are to be reported to the carrier or not (i.e. whether they
drive INTREQ0 or not). This bit defaults to 0 (interrupt request
disabled) and event interrupts are only flagged internally. That is,
you would have to poll the Event Status Register to determine if
an interrupt had occurred, and the INTREQ0 line would not be
driven. If bit 0 of this register is set to “1”, then interrupts will
drive the INTREQ0 line and permit Interrupt Select Cycles
(INTSEL) to occur. This bit is cleared following a system reset,
but not a software reset.
Writing a 1 to the bit 1 position of this register will cause a
software reset to occur (be sure to preserve the current state of
bit 0 when conducting a software reset). This bit is not stored
and merely acts as a trigger for software reset generation (this bit
will always read back as 0). The effect of a software reset is
similar to a carrier reset, except that it is not driven by the carrier.
The Interrupt Vector Register and the Interrupt Enable Bit of this
register are not cleared in response to a software reset. Bits 2-7
of this register are not used and will always read high (1‟s).
Interrupt Vector Register (Read/Write, Base + 2EH)
This 8-bit read/write register is used to store the interrupt
vector that will be served (read) during an interrupt select cycle.
In response to an interrupt select cycle, the IOS module will
execute a read of this register. Interrupts are only generated for
events while in the Enhanced Mode (see Interrupt Enable
register). This register is cleared following a system reset, but
not a software reset. Interrupts will not be reported to the carrier
