AP500/AP520/AP521 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 27 - http://www.acromag.com
- 27 -
www.acromag.com
4800
19,200
48
00
30
7200
28,800
32
00
20
9600
38,400
24
00
18
19,200
76,800
12
00
0C
28,800
115,200
8
00
08
38,400
153,600
6
00
06
57,600
230,400
4
00
04
230,400
921,600
1
00
01
3.2.5 IER - Interrupt Enable Register (R/W)
The Interrupt Enable Register is used to independently enable/ disable the
serial port interrupt sources.
Interrupts are disabled by resetting the corresponding IER bit low (0), and
enabled by setting the IER bit high (1). Disabling the interrupt system (IER
bits 7-5 and 3-0 low) also inhibits the Interrupt Status Register (ISR). In
addition to enabling the desired bits in the IER, bit-3 of the Modem Control
Register (MCR) must be set to a logic “1” to enable interrupts.
Table 3.6
Interrupt Enable
Register
IER BIT
INTERRUPT ACTION
0
0 = Disable Interrupt 1 = Enable Interrupt
This interrupt will be issued when the FIFO has reached
the programmed trigger level or is cleared when the FIFO
drops below the trigger level in the FIFO mode of
operation. Note that the receive FIFO must also be
enabled via bit-0 of the FCR for a receive interrupt to be
issued.
1
0 = Disable Interrupt 1 = Enable Interrupt
This interrupt will be issued whenever the THR is empty
and is associated with bit-1 in the LSR.
2
0 = Disable Interrupt 1 = Enable Interrupt
This interrupt will be issued whenever a fully assembled
receive character is available.
3
0 = Disable Interrupt 1 = Enable Interrupt
Modem Status Interrupt. Since the modem input signals
