AP500/AP520/AP521 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 24 - http://www.acromag.com
- 24 -
www.acromag.com
0x1001
EFR - Enhanced Function
Register
Read/Write
0x1010
TXCNT - Transmit FIFO Level
Counter
TXTRG – Transmit FIFO Trigger
Level
Read-only
Write-only
0x1011
RXCNT- Receive FIFO Level
Counter
RXTRG – Receiver FIFO Trigger
Level
Read-only
Write-only
0x1100
Xoff- 1 - Xoff Character 1 Xchar
Read-only
Write-only
Xon,Xoff
Rcvd. Flags
0x1101
Xoff- 2 - Xoff Character 2
Write-only
0x1110
Xon- 1 - Xon Character 1
Write-only
0x1111
Xon- 2 - Xon Character 2
Write-only
3.2.2 RHR - Receiver Holding Register (READ Only)
The Receiver Holding Register (RHR) is a serial port input data register that
receives the input data from the receiver shift register. Note that the RHR
will only receive data if the transceiver is first enabled to receive data. The
transceiver is enabled to receive data by setting bit-0 of the MCR (Modem
Control Register) to a logic “1”.
The RHR holds from 5 to 8 bits of data, as specified by the character size
programmed in the Line Control Register (LCR bits 0 & 1). If less than 8 bits
are transmitted, then data is right-justified to the LSB. If parity is used, then
LCR bit 3 (parity enable) and LCR bit 4 (type of parity) are required. Status
for the receiver is provided via the Line-Status Register (LSR). When a full
character is received (including parity and stop bits), the data-received
indication bit (bit 0) of the LSR is set to 1. The host CPU then reads the
Receiver Holding Register, which resets LSR bit 0 low. If the character is not
read prior to a new character transfer between the receiver shift register
and the receiver buffer register, the overrun-error status indication is set in
LSR bit 1. If there is a parity error, the error is indicated in LSR bit 2. If a
stop bit is not detected, a framing error indication is set in bit 3 of the LSR.
Serial asynchronous data is input to the receiver shift register via the receive
data line (RxD). From the idle state, this line is monitored for a high-to-low
transition (start bit). When the start bit is detected, a counter is reset and
counts the 16x clock to 7-1/2 (which is the center of the start bit). The start
bit is judged valid if RxD is still low at this point. This is known as false start-
bit detection. By verifying the start bit in this manner, it helps to prevent
the receiver from assembling an invalid data character due to a low-going
noise spike on RxD. If the data on RxD is a symmetrical square wave, the
center of the data cells will occur /-3.125% of the actual center
(providing an error margin of 46.875%). Thus, the start bit can begin as
much as one 16x clock cycle prior to being detected.
