AP500/AP520/AP521 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 29 - http://www.acromag.com
- 29 -
www.acromag.com
LEVEL
Bit5 to Bit0
1
000110
Receiver Line Status (see LSR bits 1-4)
2
000100
Received Data Ready or Trigger Level
reached.
2
001100
Receive Data Time Out.
3
000010
Transmitter Holding Register Empty
4
000000
MSR (Modem Status Register)
5
010000
Received Xoff signal special character
6
100000
CTS, RTS change of state
Note that ISR bit 0 can be used to indicate whether an interrupt is pending
(bit 0 low when interrupt is pending). ISR bits 1 & 2 are used to indicate the
highest priority interrupt pending. ISR bit 3 is always logic 0 in the 16C450
mode. ISR bit 3 is set along with bit 2 when in the FIFO mode and a timeout
interrupt is pending. Bit 4 set indicates a Xoff/special character detected
interrupt pending. Bit 5 indicates a pending interrupt due to a change of
state on the CTS or RTS signals.
Bits 6 and 7 are set when bit 0 of the FIFO Control Register is set to 1. A
power-up or system reset sets ISR bit 0 to logic “1”, and bits 1 to 7 to logic
“0”.
3.2.7 FCR - FIFO Control Register (WRITE Only)
This write-only register is used to enable and clear the FIFO buffers, set the
transmit/receive FIFO trigger levels, and select the type of DMA signaling.
Table 3.8 FIFO Control
Register
FCR BIT FUNCTION
0
When set to “1”, this bit enables both the Tx and Rx FIFO’s.
All bytes in both FIFO’s can be cleared by resetting this bit to
0. Data is cleared automatically from the FIFO’s when
changing from FIFO mode to the alternate (16C450) mode and
visa-versa. This bit must be a “1” when other FCR bits are
written to or they will not be programmed.
1
When set to “1”, this bit clears all bytes in the Rx-FIFO and the
resets counter logic to 0 (this does not clear the shift register).
2
When set to “1”, this bit clears all bytes in the Tx-FIFO and
resets the counter logic to 0 (this does not clear the shift
register).
3
When set to “1”, this bit sets DMA Signal from Mode 0 to
