Acromag 900EN-S005 User Manual Download

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BusWorks

900EN-S005 Ethernet Switch User’s Manual Ethernet I/O

__________________________________________________________________

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Acromag, Inc. Tel:248-624-1541 Fax:248-624-9234 Email:

[email protected]

http://www.acromag.com

Port Control 12 and 13 registers 28 & 29, and Port Status 0 contents can be
accessed by MIIM (MDC/MDIO) interface via the standard MIIM register
definition.

REG

DESCRIPTION

DEF

1CH

Port 1 Control 12

5DH

Bit

Function

Disable Auto-Negotiation (AN):
1=Disable Auto-Negotiation – Speed and Duplex

are decided by bits 6 & 5 of this register.

0=Auto-Negotiation is ON.

Force Speed (w/ Auto-Negotiation Off):
1=Force 100baseT if Auto-Neg is disabled via bit 7.
0=Force 10baseT if Auto-Neg is disabled via bit 7.

Force Duplex (w/ Auto-Negotiation Off):
1=Force Full-Duplex if Auto-Neg is disabled, or

Auto-Neg is enabled but failed.

0=Force Half-Duplex if Auto-Neg is disabled, or

Auto-Neg is enabled but failed.

Note that this function may be optionally
configured via DIP switch S1-7 for port 4 only
(ON=Half-Duplex) following reset.

Advertise Flow-Control Capability:
1=Advertise Flow-Control Capability.
0=Suppress Flow-Control Capability from

transmission to link partner.

Advertise 100BaseT Full-Duplex Capability:
1=Advertise 100BaseT Full-Duplex capability.
0=Suppress 100BaseT Full-Duplex capability from

transmission to link partner

Advertise 100BaseT Half-Duplex Capability:
1=Advertise 100BaseT Half-Duplex capability.
0=Suppress 100BaseT Half-Duplex capability from

transmission to link partner

Advertise 10BaseT Full-Duplex Capability:
1=Advertise 10BaseT Full-Duplex Capability.
0=Suppress 10BaseT Full-Duplex Capability from

transmission to Link Partner

Advertise 10BaseT Half-Duplex Capability:
1=Advertise 10BaseT Half-Duplex Capability.
0=Suppress 10BaseT Half-Duplex Capability from

transmission to Link Partner

2CH

Port 2 Control 12 (Port 1 Control 12 Description)

5FH

3CH

Port 3 Control 12 (Port 1 Control 12 Description)

5FH

4CH

Port 4 Control 12 (Port 1 Control 12 Description)

5FH

5CH

Port 5 Control 12 (Port 1 Control 12 Description)

5FH

Register Map

Summary of Contents for 900EN-S005

Page 1: ...Port 10 100M Ethernet Switch USER S MANUAL ACROMAG INCORPORATED Tel 248 624 1541 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A Copyright 2003 Acromag Inc Printed in th...

Page 2: ...Box DIP Switch Mode 18 EEPROM Mode 19 EEPROM Program Utility keeprom exe 20 EEPROM Register Map 22 SPI Slave Mode 40 TERMS AND CONCEPTS 41 Auto MDI MDI X Crossover 41 Auto Negotiation Auto Sense 42 A...

Page 3: ...ING OPTIONS REFER TO MANUAL The port status LED indicators are programmable via DIP switches and have two possible display modes that combine indication of speed collision duplex link and activity By...

Page 4: ...Polarity Automatic Half Full Duplex Automatic 10M 100M Automatic Address Learning Automatic Address Migration Automatic Address Aging using 5 minute period 300 75s Flow Controls Enabled Half Duplex B...

Page 5: ...al configuration at power up the operation of the port LED s and how the program port interface P1 is to operate Set S2 switches UP to turn them ON and DOWN for OFF Interface Selection Switch Bank 2 S...

Page 6: ...SET POWER ON ON DIP SWITCHES PUSH BUTTON RESET For an explanation of unfamiliar terms or modes of operation please refer to the Technical Reference section of this manual Socket P1 is located on top o...

Page 7: ...ult LED Mode 0 Link Activity LED Once auto negotiation has completed the Link Activity LED will be ON to indicate Link status This LED will blink ON OFF intermittently to indicate activity when data i...

Page 8: ...x channels pairs as required As such a straight through or crossover cable can be used to connect to any port of this device However it is not good practice to use crossover cables when wiring to a sw...

Page 9: ...T CABLE MDI X AS BOTH THE PC AND THE 9XXEN MODULE ETHERNET PORTS ARE WIRED MDI ETHERNET SWITCHES AND HUBS ARE WIRED MDI X THE ACROMAG ETHERNET SWITCH IS AUTOMATIC MDI MDI X AND ELIMINATES THE NEED FOR...

Page 10: ...is limited to 100 meters using approved cable Good practice further limits segment length to 80 or 80 meters Network cable may be picking up noise Try using Category 5E shielded cable and shielded RJ...

Page 11: ...and cabling problems and may also compile Management Information Base MIB data similar to that shown in the table below This table gives additional troubleshooting information for common MIB statisti...

Page 12: ...t and devices on this segment RxJabbers Stop that incessant jabbering shut up and listen This counts the number of frames larger than the maximum packet size of 1522 bytes or 1536 bytes depending on t...

Page 13: ...cting the node may be too long it must be less than 100M Otherwise there may be a duplex mismatch between the switch port and the connected node RxCRCerror RxAlignmentError These stats count the numbe...

Page 14: ...mitting at the same time again but collisions may still occur and this process will repeat itself until the packets finally pass onto the network or the packets may be discarded after 16 consecutive c...

Page 15: ...us and minus polarities for the differential Tx Rx channel pairs Unmanaged Stand Alone Operation No PC for basic operation Wire Speed Receive and Transmit Non Blocking Switch Allows simultaneous trans...

Page 16: ...e network distance Switches split networks into separate collision domains at each port Switches provides determinism by reducing collisions Switches increases network bandwidth throughput Switches ca...

Page 17: ...iated port number up to 1024 MAC addresses are stored in high speed SRAM However until the switch actually learns the port a particular address resides at the first packet it forwards this traffic to...

Page 18: ...al reserved for factory use The second and third levels also require an optional cable Acromag model 5035 365 and configuration software This section of the manual will explain some of the alternate o...

Page 19: ...e settings of the other switches as opposed to the settings configured in the corresponding EEPROM registers see Register Map For options not directly addressed by a DIP switch the defaults noted in t...

Page 20: ...ion The actual data that traverses the serial line changes during the clock low time This interface is compatible with the Atmel AT24C02 EEPROM and further timing and data sequences can be found in th...

Page 21: ...t takes two hex digits to represent eight register bits Use this table and divide each register into two 4 bit numbers in order to determine what to write to a register Note that any changes you make...

Page 22: ...tware To write data to the EEPROM registers you will need to refer to the EEPROM Register Map that follows You will have to enter data in byte form using two hexadecimal digits to represent the conten...

Page 23: ...12 15 0CH 0FH Reserved Do Not Modify 16 29 10H 1DH Port 1 Control Registers 30 31 1EH 2FH Port 1 Status Registers Read Only 32 45 20H 2DH Port 2 Control Registers 46 47 2EH 2FH Port 2 Status Registers...

Page 24: ...ess an image of registers 0 127 within the ASIC However in SPI Mode the system should first configure all desired settings then enable the switch via this bit Recall that DIP Switch S2 3 is used to se...

Page 25: ...port is unplugged all addresses are automatically aged out 0 Do not allow fast aging Aging period remains 300 75 seconds 1 3 03H Global Control 1 04H Bit Function 7 Pass ALL Frames Enable 1 Switch al...

Page 26: ...cannot cross VLAN boundary 0 Unicast packets excluding unknown multicast broadcast can cross VLAN boundary 1 6 Multicast Storm Protection Disable 1 Broadcast Storm Protection does not include multica...

Page 27: ...2 bytes for tagged packets not including packets w STPID from CPU to ports 1 4 or up to including 1518 bytes for untagged packets Any packets larger than the specifed maximum are dropped This function...

Page 28: ...er source port or destination port must match This is the mode used to implement Rx only sniff 0 6 06H Global Control 4 00H Bit Function 7 Switch MII Back Pressure Enable 1 Enable half duplex back pre...

Page 29: ...Do Not Read Write 24H 11 0BH Global Control 9 00H Bit Function 7 2 Reserved For Factory Testing Do Not Write 0 1 LED Mode 0 MODE 0 1 MODE 1 0 1 LED 0 Red Speed Full Duplex LED 1 Yel Full Dx Collision...

Page 30: ...ort the switch will add 802 1Q tags to packets without 802 1Q tags when received The switch will NOT add tags to packets already tagged The tag inserted is the ingress port VLAN ID port VID 0 Disable...

Page 31: ...rol 1 See Port 1 Control 1 Description 1FH 18 12H Port 1 Control 2 0EH 06H Bit Function 7 Reserved Do Not Write 0 6 Ingress VLAN Filtering 1 The switch will discard packets whose VLAN ID VID port memb...

Page 32: ...0 0 34 22H Port 2 Control 2 See Port 1 Control 2 Description 0EH 50 32H Port 3 Control 2 See Port 1 Control 2 Description 0EH 66 42H Port 4 Control 2 See Port 1 Control 2 Description 0EH 82 52H Port...

Page 33: ...5 See Port 1 Control 5 Description 00H 85 55H Port 5 Control 5 See Port 1 Control 5 Description 00H 22 16H Port 1 Control 6 00H Bit Function 7 0 Transmit LOW Priority Rate Control 7 0 This byte along...

Page 34: ...10 bits 7 4 form a 12 bit field to determine how many 32Kbps low priority blocks can be received in a unit of 32K bits or 4K bytes in a one second period 0 41 29H Port 2 Control 9 See Port 1 Control...

Page 35: ...control 0 4 Low Priority Receive Rate Flow Control Enable 1 Flow control may be asserted if the port s low priority receive rate is exceeded 0 Flow control is not asserted if the port s low priority r...

Page 36: ...d but failed Note that this function may be optionally configured via DIP switch S1 7 for port 4 only ON Half Duplex following reset 0 4 Advertise Flow Control Capability 1 Advertise Flow Control Capa...

Page 37: ...loop back the PHY Tx channel to its Rx channel 0 Normal operation 0 45 2DH Port 2 Control 13 Port 1 Control 13 Description 00H 61 3DH Port 3 Control 13 Port 1 Control 13 Description 00H 77 4DH Port 4...

Page 38: ...6 bit TOS field in the IP header The most significant 6 bits of the TOS field are fully decoded into 64 possibilities and the singular code that results is compared against the corresponding bit in t...

Page 39: ...le selected 01 VLAN table selected 10 Dynamic address table selected 11 MIB counter selected 00 1 0 Indirect Access High Bits 9 8 of indirect address 00 111 6FH Indirect Access Control 1 SPI Mode Only...

Page 40: ...tus LED s The relative function of these LED s is determined by DIP switch S2 4 in DIP Switch Mode or bit 1 of register 11 The following table gives the default LED indication mode 0 DIP switch S2 4 O...

Page 41: ...1 and S2 3 ON to set the module to SPI Slave Mode ON Additionally make sure DIP switch S2 2 is OFF to enable SPI access Refer to this section for more information on unfamiliar terms topics and operat...

Page 42: ...lity Port Control 12 Bit 3 Advertise 10baseT Full Duplex Capability Port Control 12 Bit 3 Advertise 10baseT Half Duplex Capability Port Status 0 Bit 3 Read for 100baseT Full Duplex Capable Port Status...

Page 43: ...rame at any time Normally each device will first sense whether the line is idle and available for use channel clear If it is clear the device will begin to transmit its first frame During this transmi...

Page 44: ...alid packet in Ethernet 64 bytes or 512 bits of data However if a transmit packet has a collision after 512 bit times of the transmission the packet will be dropped Late collisions refer to collisions...

Page 45: ...nimum transmission time for a complete frame must be at least one slot time Further the time required for collisions to propagate the entire network must be less than one slot time As such a station c...

Page 46: ...if a given network connection is permissible by making sure that the one way delay between the two furthest nodes is less than half the slot time 25 6us 10BaseT or 2 56us 100BaseT Times given above a...

Page 47: ...eck Search Dynamic Table Search Static Table IGMP Process Spanning Tree Process Not Supported Network Time Parameter 10BaseT 10MHz 100BaseT 100MHz Bit Time BT 100ns 10ns Slot Time 512BT 51 2us 512BT 5...

Page 48: ...Pause Scheme is used For half duplex segments the back pressure approach is used Full Duplex Flow Control Full duplex flow control is enabled by default but may be disabled via DIP switch S1 2 Per IE...

Page 49: ...on time to clear its receive buffer by sending packets already in its queue For carrier sense the method used in 900EN S005 if back pressure is required the switch will send preambles to defer transmi...

Page 50: ...orwarded to all ports except the source ingress port What can happen is that if a broadcast multicast or unicast message is transmitted at a port all other ports can become flooded with this transmiss...

Page 51: ...interval expires If the rate limit is programmed greater than or equal to 128Kbps and the byte counter is 8Kbytes below the limit this flow control will still be triggered If the rate limit is program...

Page 52: ...gh priority blocks can be received in a unit of 32K bits or 4K bytes in a one second period Port Control 9 bits 7 0 and Port Control 10 bits 7 4 Receive LOW Priority Rate Control A 12 bit number that...

Page 53: ...possibilities and each resultant singular code is compared against the corresponding bit in the DSCP register If the register bit is 1 the priority is high and low if 0 Each port has an enable port DS...

Page 54: ...ed to classify priority of incoming packets by comparing it against the User Priority Packet is high priority if user priority is greater than or equal to this number and low priority if less than thi...

Page 55: ...twork segment or broadcast domain Port based VLAN s allow the end stations at different switch ports of the same switch to be included in a virtual network segment by grouping together one or more por...

Page 56: ...at this port Set to include a port clear to exclude a port You must also include this port the ingress port The five ports of this switch are applied to bits 4 0 as follows Bit 4 Port 5 Bit 3 Port 4...

Page 57: ...t 1 Port 3 Port 5 VLAN 5 Port 5 to All Membership Bits 4 0 11111 VLAN 4 Port 4 to Port 5 Membership Bits 4 0 11000 Note No broadcast traffic from Port 1 will go to Port 4 or Port 4 to Port 1 VLAN 1 Po...

Page 58: ...over Data Rate Auto negotiated 10Mbps or 100Mbps Duplex Auto negotiated Full or Half Duplex Compliance IEEE 802 3 802 3u 802 3x Port Status Indicators Three LED s per port red yellow and green Two ind...

Page 59: ...evice to be modified and optional modes of operation selected These switches are located in the top opening adjacent to the power terminals and reset button DIP switch S2 1 must be OFF to enable use o...

Page 60: ...ess table and the MIB counters Use of the SPI interface in SPI Slave Mode is reserved for factory use only and is not covered in this manual Connector P1 This buffered combination I 2 C SPI interface...

Page 61: ...torage Temperature 40 C to 85 C 40 F to 185 F Relative Humidity 5 to 95 non condensing Power Requirements Non polarized 15 36V DC SELV Safety Extra Low Voltage 2 6W Observe proper polarity See table f...

Page 62: ...te measures Power Indicator Green LED ON indicates power internal 3 3V rail OK Port Status Indicators Three LED s per port red yellow and green Two indication modes combine speed link status activity...

Page 63: ...ire that encircles the outer jacket A double shielded version adds an outer wire screen that surrounds the foil shield and also functions as a drain wire The drain wire or wire screen typically makes...

Page 64: ...8CSR Regal Electronics www regalusa com see shielded plug model 1003B 8P8CSR C5 Complete premium double shielded Category 5e standard and crossover cables in variable lengths can be obtained from Lumb...

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