BusWorks
®
900EN-S005 Ethernet Switch User’s Manual Ethernet I/O
___________________________________________________________________
_______________________________________________________________________________________
Acromag, Inc. Tel:248-624-1541 Fax:248-624-9234 Email:
http://www.acromag.com
25
REG
DESCRIPTION
DEF
2
02H
Global Control 0…continued
4CH
Bit
Function
2
Buffer Share Mode:
1=Share buffer pool among all ports and allow any
port to use more buffer than allocated when other
ports are not busy (default).
0=Restrict each port to 1/5 of available buffer pool.
1
1
UNH Mode:
1=Switch will drop packets with 8808H in T/L field, or
with DA=01-08-C2-00-00-01.
0=Switch will drop packets qualified as flow control
packets.
0
0
Link
Change
Age:
1=A change from “link” to “no link” will cause fast
aging (less than 800us) of addresses. After an
age cycle is complete, the aging logic will return to
normal (300±75 seconds).
Note:
If any port is unplugged, all addresses are
automatically aged out.
0=Do not allow fast aging. Aging period remains
(300±75 seconds).
1
3
03H
Global Control 1
04H
Bit
Function
7
Pass ALL Frames Enable:
1=Switch all packets including bad packets. Used
for debugging purposes only and works in
conjunction with sniffer mode.
0=Do not switch bad packets.
0
6
Reserved
0
5
IEEE 802.3x Transmit Flow Control Disable:
1=Do not enable transmit flow control, no matter
what the auto-negotiation result is.
0=Enable transmit flow control based on auto-
negotiation result.
This function may optionally be controlled via
DIP switch S1-2 for both receive and transmit
combined, but the Tx/Rx flow control can be
programmed independently via bits 5 & 4 of this
register.
0/1
4
IEEE 802.3x Receive Flow Control Disable:
1=Do not enable receive flow control, no matter
what the auto-negotiation result is.
0=Enable transmit flow control based on auto-
negotiation result.
This function may optionally be controlled via
DIP switch S1-2 for both receive and transmit
combined, but the Tx/Rx flow control can be
programmed independently via bits 5 & 4 of this
register.
0/1
Register Map