BusWorks
®
900EN-S005 Ethernet Switch User’s Manual Ethernet I/O
__________________________________________________________________
_______________________________________________________________________________________
Acromag, Inc. Tel:248-624-1541 Fax:248-624-9234 Email:
http://www.acromag.com
24
REG
DESCRIPTION
DEF
0
00H
Chip ID0 Register – Chip Family Identification
95H
Bit
Function
7-0
Chip Family (Treat as Read Only) – Contents of this
register byte is checked at power-on/reset along with
bits 7:4 of register 1. The internal switch engine will
use EEPROM register settings to determine its
operation if this register contains 95H and bits 7..4
of register 1 contain 0H. Otherwise, it will use
internal defaults and ignore the EEPROM contents.
95H
1
01H
Chip ID1 Register / Start Switch:
04H
Bit
Function
7-4
Chip Family (Read Only) – “0000” designates “M”
series chip (95M) family. The contents of this nibble
is checked at power-on/reset along with bits 7:0 of
register 0. The internal switch engine will use
EEPROM register settings to determine its operation
if bits 7..4 of this register contain 0000 and register 0
contains 95H. Otherwise, it will use internal defaults
and ignore the EEPROM contents.
0000
3-1
Read Only - Chip Revision ID (Currently 2).
010
0
Read/Write - Start Switch For SPI Slave Mode Only:
1=Start switch automatically in SPI Slave Mode;
0=Do Not Start switch in SPI Slave Mode.
In SPI Slave Mode, an external master can
randomly access an image of registers 0-127 within
the ASIC. However, in SPI Mode the system should
first configure all desired settings, then enable the
switch via this bit. Recall that DIP Switch S2-3 is
used to select the serial mode. DIP switch S2-1 is
used to enable communication with the EEPROM. If
switch S2-3 is OFF, then the I
2
C master mode is
selected and the internal switch ASIC will start
automatically after first trying to read the EEPROM
contents. If the EEPROM does not exist or is
disabled (DIP switch S2-1 is OFF), the switch ASIC
will use default values for all internal parameters.
Note that some default values can be set by
changing DIP switches and resetting the module. If
the EEPROM is present (DIP switch S2-1 is ON),
the contents of the EEPROM will be checked. If
EEPROM register 0 = 95H and register 1 bits [7:4] =
0000, then the contents of the EEPROM will over-
ride register default values and DIP switch settings.
0
2
02H
Global Control 0
4CH
Bit
Function
7
Reserved
0
6-4
802.1p Base Priority: Used to classify priority for
incoming 802.1Q packets. The “User-Priority” is
compared against this 3 bit value. If it is greater
than or equal to, then it is classified as high priority.
If it is less, then it is classified as low priority.
100
3
1=Enable PHY MII interface; 0=Tri-state all MII
interface outputs.
This model does not implement the MII interface.
1
Register Map
The DEF settings noted in the
Register Map represent the
defaults that apply in EEPROM
Mode and reflect the contents
contained in the data file
(default95M.dat) used by the
EEPROM program software.
In some cases (noted), these
defaults will differ in DIP switch
Mode with all switches OFF.
