Acer Aspire 1420P Series, Service Manual

Page: 166 / 216

156 Chapter 4
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14 Verify burst length of 8 is supported by all DIMMs
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15 Determine the smallest tWR supported by all DIMMs
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16 Determine DIMM size parameters
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17 Program the correct system memory frequency
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18 Determine and set the mode of operation for the memory channels
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19 Program clock crossing registers
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20 Disable Fast Dispatch
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21 Program the DRAM Row Attributes and DRAM Row Boundary registers
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22 Program the DRAM Bank Architecture register
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23 Program the DRAM Timing & and DRAM Control registers
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24 Program ODT
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25 Perform steps required before memory init
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26 Program the receive enable reference timing control register
Program the DLL Timing Control Registers, RCOMP settings
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27 Enable DRAM Channel I/O Buffers
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28 Enable all clocks on populated rows
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29 Perform JEDEC memory initialization for all memory rows
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30
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31 Perform steps required after memory init
Program DRAM throttling and throttling event registers
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32 Setup DRAM control register for normal operation and enable
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33 Enable RCOMP
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34 Clear DRAM initialization bit in the SB
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35 Initialization Sequence Completed, program graphic clocks
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AF
Disable access to the XMM registers