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Manual 104-AIO16A and 104-AIO16E

19

Base A 12

(read)

A/D, DAC, FIFO Status Flags

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

fifoFull halfFull empty dac1 dac0 gainMode

single-ended

bipolar

Reading from this address will show the status of the following flags:

bipolar

Æ

‘0’ = jumpers set to unipolar

‘1’ = jumpers set to bipolar

single-ended

Æ

‘0’ = jumpers set to differential ‘1’ = jumpers set to single-ended

gainMode

Æ

‘0’ = jumpers set to GNL

‘1’ = jumpers set to GNH

dac0

Æ

‘0’ = DAC 0 has 0-10V range

‘1’ = DAC 0 has 0-5V range

dac1

Æ

‘0’ = DAC 1 has 0-10V range

‘1’ = DAC 1 has 0-5V range

empty

Æ

‘0’ = A/D Data FIFO is empty

‘1’ = A/D Data FIFO is not empty

halfFull

Æ

‘0’ = A/D FIFO is at least half full ‘1’ = A/D FIFO is not at least half full

fifoFull

Æ

‘0’ = A/D Data FIFO is full

‘1’ = A/D Data FIFO is not full

Base A 13

(read/write)

IRQ Configuration and Status

Base A 13 write

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

X X X X

fullIrqEn

halfFullIrqEn

eosIrqEn

eocIrqEn

Writing to this address will configure the IRQs for End of Conversion (EOC), End of Scan (EOS), A/D
Data FIFO at least half full, and A/D Data FIFO full. Below are the IRQ enable bit patterns:

eocIrqEn

Æ

‘0’ = disable the EOC IRQ

‘1’ = enable the EOC IRQ

eosIrqEn

Æ

‘0’ = disable the EOS IRQ

‘1’ = enable the EOS IRQ

halfFullIrqEn

Æ

‘0’ = disable the A/D Data FIFO ‘1’ = enable the A/D Data FIFO

is at least half full IRQ

is at least half full IRQ

fullIrqEn

Æ

‘0’ = disable the A/D Data FIFO ‘1’ = enable the A/D Data FIFO

full IRQ

full IRQ

Base A 13 read

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

fullIrq

halfFullIrq

eosIrq

eocIrq

X X X X

Once any of the above IRQ enables are set to ‘1’, the corresponding condition will cause an IRQ to be
generated. All four enables can be set at the same time. A read of this address allows the ability to see
which IRQ flag generated the IRQ. Below are the IRQ flags:

eocIrq

Æ

‘0’ = no EOC IRQ occurred

‘1’ = EOC IRQ occurred

eosIrq

Æ

‘0’ = no EOS IRQ occurred

‘1’ = EOS IRQ occurred

halfFullIrq

Æ

‘0’ = no A/D FIFO is at least

‘1’ = A/D FIFO is at least

half full IRQ occurred

half full IRQ occurred

fullIrq

Æ

‘0’ = no FIFO full IRQ occurred ‘1’ = FIFO full IRQ occurred

Reading this address also clears any of the IRQ flags that are set.

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Summary of Contents for 104-AIO16A

Page 1: ...0623 Roselle Street San Diego CA 92121 858 550 9559 Fax 858 550 7322 contactus accesio com www accesio com 104 AIO16A and 104 AIO16E PC 104 HIGH PERFORMANCE ANALOG I O BOARDs USER MANUAL M104 AIO16A A1k ...

Page 2: ... of ACCES nor the rights of others IBM PC PC XT and PC AT are registered trademarks of the International Business Machines Corporation Printed in USA Copyright 2008 by ACCES I O Products Inc 10623 Roselle Street San Diego CA 92121 All rights reserved WARNING ALWAYS CONNECT AND DISCONNECT YOUR FIELD CABLING WITH THE COMPUTER POWER OFF ALWAYS TURN COMPUTER POWER OFF BEFORE INSTALLING A BOARD CONNECT...

Page 3: ...her manufacturers in the industry Equipment Not Manufactured by ACCES Equipment provided but not manufactured by ACCES is warranted and will be repaired according to the terms and conditions of the respective equipment manufacturer s warranty General Under this Warranty liability of ACCES is limited to replacing repairing or issuing credit at ACCES discretion for any products which are proved to b...

Page 4: ...guration 13 Chapter 4 Base Address Selection 14 Table 4 1 Hex Conversion 14 Chapter 5 Programming 15 Table 5 1 Register Definitions 15 Writing to the EEPROM 21 Reading from the EEPROM 22 Chapter 6 Connector Pin Assignments 25 Table 6 1 P1 26 pin Right Angle Header Analog Inputs Analog Outputs 25 Table 6 2 P2 44 pin Right Angle Header Digital I O Counter Timers 26 Table 6 3 P3 8 pin Right Angle Hea...

Page 5: ...4 module size and mounting compatibility Applications z Equipment monitoring z Environmental measurements z Embedded data acquisition z Education Laboratory Functional Description This product is a PC 104 based Analog to Digital converter board with 16 single ended or 8 differential analog inputs The board is capable of sampling speeds up to 500kHz Analog input channels are enabled as a consecutiv...

Page 6: ... CONTAINED IN 8254 Figure 1 1 Block Diagram Analog Inputs There are a total of 16 single ended or 8 differential analog inputs on this board A consecutive set of channels are enabled disabled by software This set of channels is constructed by a start and end channel Sampling begins on the start channel and continues through every successive channel until the end channel is sampled Once the end cha...

Page 7: ...channel multiple times at 500kHz Quickly taking several samples from the same channel allows the signal to be averaged Averaging a signal can greatly reduce the noise injected by both the signal and the board system The oversample range is from 0 to 255 software selectable and applies to every channel within the enabled set A channel is always sampled once plus the number of oversamples that was c...

Page 8: ...l calibration potentiometers are serial devices with data being entered bit by bit Although the details of writing bit by bit are described in Appendix B it is expected that data will be loaded using a software subroutine Make sure that the correct calibration constants are loaded into the digital potentiometers before using the analog outputs Refer to Appendix B for calibrating the DACs Lastly th...

Page 9: ...ize S0x Special number designator application specific contact factory o Examples latching I O connectors configuration jumpers factory set Included with your board The following items are included with your shipment Please take time now to ensure that no items are damaged or missing 1 PC 104 Analog and Digital I O Module 2 Software Master CD PDF user manual installed with product package 3 Printe...

Page 10: ...the on screen prompts to install the software for this board LINUX a Please refer to linux htm on the CD ROM for information on installing under linux Hardware Installation Install the software package and set all hardware configuration jumpers refer to Chapter 3 Option Selection before plugging the hardware into the system The SETUP Program can also be used to assist in configuring jumpers on the...

Page 11: ...e stack ensuring proper alignment of the pins before completely seating the connectors together 5 Install I O cables onto the board s I O connectors and proceed to secure the stack together or repeat steps 3 5 until all boards are installed using the selected mounting hardware 6 Check that all connections in your system are correct and secure then power up the system 7 Run one of the provided samp...

Page 12: ...r with a 1k sample FIFO There is an optional version of the board that provides an onboard DC DC converter If your PC 104 stack has 5V and 12V available a DC DC converter is not needed IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 BIPOLAR UNIPOLAR GNH GNL DIFF S E 0 10V 0 5V DAC B DAC A A5 A6 A7 A8 A9 P2 Pin 1 P1 Pin 1 P3 DC DC Option 104 Bus EXT P3 12V SOURCE SELECT Figure 3 1 Optio...

Page 13: ...S 120h 13Bh YES YES YES 140h 15Bh YES YES 160h 17Bh YES YES YES 180h 19Bh YES YES 1A0h 1BBh YES YES 1C0h 1DBh YES 1E0h 1FBh YES YES YES YES 200h 21Bh YES YES YES 220h 23Bh YES YES YES 240h 25Bh YES YES 260h 27Bh YES YES YES 280h 29Bh YES YES 2A0h 2BBh YES YES 2C0h 2DBh YES 2E0h 2FBh YES YES YES 300h 31Bh YES YES 320h 33Bh YES YES 340h 35Bh YES 360h 37Bh YES YES 380h 39Bh YES 3A0h 3BBh YES 3C0h 3DB...

Page 14: ... the board For example as illustrated below switch selection corresponds to hex 2C0 or binary 10 110x xxxx The xxxxx represents address lines A4 through A0 used on the board to select individual registers as described in Chapter 5 Programming Hex Representation 2 C Conversion Factors 2 1 8 4 2 Binary Representation 1 0 1 1 0 Jumper Installed NO YES NO NO YES Jumper Label A9 A8 A7 A6 A5 Table 4 1 H...

Page 15: ...bled if the A D Start Source is either Timer Start or External Start Trigger If the A D Start Source is Software Start conversions will begin after a write to Base Address 1 6 Read A D data from the A D Data FIFO with a read from Base Address 0 1 It is helpful to use the flags in Base Address 12 and the IRQ flags in Base Address 13 when deciding to read A D data Offset Write Function Read Function...

Page 16: ...ase Address 1 The byte read from Base Address 0 must be done before the byte read from Base Address 1 or the lower data byte will be lost Base Address 1 write A D Software Start Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Software start Writing any value to this address will begin one A D Start Base Address 2 5 write A D Programmable Gain Configuration Base Address 2 Bit 7 Bit 6 Bit 5 Bit 4 Bi...

Page 17: ...r Timer 0 is fully programmable for general use Counter Timer 1 2 are concatenated together output of Counter Timer 1 is routed to the clock input of Counter Timer 2 The concatenated Counter Timer 1 2 are used for A D Start both Timer Start and External Start Trigger The output of Counter Timer 2 is the source for the aforementioned A D Starts The output of Counter Timer 2 is available on Pin 43 o...

Page 18: ... Writing a 1 to Bit 0 will set the DAC simultaneous bit This causes both DACs to be updated on a write to DAC 1 Base Address 11 write A D Start Counter Timer 0 Clock Configuration Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X clkSrc startEdge startType startSource1 startSource0 Writing to this address will configure the A D Start Source A D Start Type A D Start as rising or falling edge an...

Page 19: ...figure the IRQs for End of Conversion EOC End of Scan EOS A D Data FIFO at least half full and A D Data FIFO full Below are the IRQ enable bit patterns eocIrqEn Æ 0 disable the EOC IRQ 1 enable the EOC IRQ eosIrqEn Æ 0 disable the EOS IRQ 1 enable the EOS IRQ halfFullIrqEn Æ 0 disable the A D Data FIFO 1 enable the A D Data FIFO is at least half full IRQ is at least half full IRQ fullIrqEn Æ 0 dis...

Page 20: ...s address configures the input output direction for Ports A and B A 1 must always be written to bit 7 when configuring Below are the Port direction bits modeSetFlag Æ 0 configuration not enabled 1 configuration enabled portADir Æ 0 Port A is output 1 Port A is input default portBDir Æ 0 Port B is output 1 Port B is input default Base Address 18 read write EEPROM access Base Address 18 read Bit 7 B...

Page 21: ...1 Bit 7 should be bit D12 of data Always set D0 to 1 15 1xxxxxx1 81 Bit 7 should be bit D11 of data Always set D0 to 1 16 0xxxxxx1 01 Bit 7 should be bit D10 of data Always set D0 to 1 17 1xxxxxx1 81 Bit 7 should be bit D9 of data Always set D0 to 1 18 0xxxxxx1 01 Bit 7 should be bit D8 of data Always set D0 to 1 19 0xxxxxx1 01 Bit 7 should be bit D7 of data Always set D0 to 1 20 1xxxxxx1 81 Bit 7...

Page 22: ...ntains bit D12 from the word at the specified address Read 5 D7 contains bit D11 from the word at the specified address Read 6 D7 contains bit D10 from the word at the specified address Read 7 D7 contains bit D9 from the word at the specified address Read 8 D7 contains bit D8 from the word at the specified address Read 9 D7 contains bit D7 from the word at the specified address Read 10 D7 contains...

Page 23: ...performed Write Value Description 1 1xxxxxx0 80 Enable code Always write 80 as the 1st byte 2 0xxxxxx1 01 3 1xxxxxx1 81 These two bits are the address of the potentiometer to write 00 is A D offset 01 is gain 10 is DAC0 gain 11 is DAC1 gain Write 2 is MSB Write 3 is LSB 4 0xxxxxx1 01 MSB of data Bit D7 of Write 4 should be the D7 bit of the calibration correction value you are loading 5 1xxxxxx1 8...

Page 24: ...l Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 104E 104A Reading from this address will indicate the presence and model number or absence of the board 104A Æ 0 N A 1 104A model detected Byte value 01 104E Æ 0 N A 1 104E model detected Byte value 02 No card detected Byte value FF ...

Page 25: ...ingled ended or Channel 3 differential non inverting input 12 AGND Analog Ground 13 Ch4 SE Ch4 DIFF Channel 4 Singled ended or Channel 4 differential non inverting input 14 Ch12 SE Ch4 DIFF Channel 12 Single ended or Channel 4 differential inverting input 15 AGND Analog Ground 16 Ch13 SE Ch5 DIFF Channel 13 Single ended or Channel 5 differential inverting input 17 Ch5 SE Ch5 DIFF Channel 5 Singled...

Page 26: ... 12 Digital I O Bit 12 pulled up 26 DGND Digital Ground 27 DIO 13 Digital I O Bit 13 pulled up 28 DGND Digital Ground 29 DIO 14 Digital I O Bit 14 pulled up 30 DGND Digital Ground 31 DIO 15 Digital I O Bit 15 pulled up 32 DGND Digital Ground 33 Unused No connection 34 DGND Digital Ground 35 KEY 36 KEY 37 Counter Timer 0 Clock 8254 Counter Timer 0 Clock input pulled up 38 DGND Digital Ground 39 Ext...

Page 27: ...dB 400kHz Analog Outputs Channels 2 Resolution 12 bit Voltage Ranges 0 5V 0 10V jumper selectable Conversion Frequency 100k conversions sec Simultaneous Update Yes Digital I O Type 8255 Port A and Port B only Lines 16 programmable as inputs or outputs in groups of 8 pulled up Input voltage Logic low 0V min to 0 8V max Logic high 2V min to 5V max Output voltage Logic low 0V min to 0 55V max Logic h...

Page 28: ...r the counter is loaded the output is set low and will remain low until the counter decrements to zero The output then goes high and remains high until a new count is loaded into the counter A trigger enables the counter to start decrementing Mode 1 Retriggerable One Shot The output goes low on the clock pulse following a trigger to begin the one shot pulse and goes high when the counter reaches z...

Page 29: ...resses hex Base Address 8 Read Write Counter 0 Base Address 9 Read Write Counter 1 Base Address A Read Write Counter 2 Base Address B Write to Counter Control register The counters are programmed by writing a control byte into a counter control register The control byte specifies the counter to be programmed the counter mode the type of read write operation and the modulus The control byte format ...

Page 30: ...You can only rely on directly read counter data if the counting process is suspended while reading by bringing the gate low or by halting the input pulses For each counter you must specify in advance the type of read or write operation that you intend to perform You have a choice of loading reading a the high byte of the count or b the low byte of the count or c the low byte followed by the high b...

Page 31: ...s binary mode otherwise counter is in BCD mode If both STA and CNT bits in the readback command byte are set low and the RW1 and RW0 bits have both been previously set high in the counter control register thus selecting two byte reads then reading a selected counter address location will yield 1st Read Status byte 2nd Read Low byte of latched data 3rd Read High byte of latched data After any latch...

Page 32: ...lved in calibrating the board Following this is a breakdown of the 5 calibration steps for the DAC This breakdown is an engineering summary providing enough detail that someone very familiar with the board could proceed Then an in depth step by step walkthrough is provided Following this is a breakdown of the steps for the ADC Finally an in depth step by step walkthrough is provided for the ADC St...

Page 33: ...ater use First let s expand Step 1 mentioned above into its component sub steps for the DAC Step 1 Determine the Calibration Constants for the DAC 1 1 Output a value corresponding to a known voltage1 on a DAC 1 2 Measure the output value of the DAC with a DVM 1 3 Adjust the value in the digital calibration potentiometer for that DAC until the voltage read by the DVM matches the known value being o...

Page 34: ... output pin on P1 pin 25 or pin 26 for DAC 0 or DAC 1 respectively Use Pin 24 for ground The DVM should be set for DC voltage measurement Once connected the DVM should read 9 499 Volts but may not be exactly correct Remember if you re using a different known output value you should see a number near it not near 9 499 1 3 Adjust the value in the digital calibration potentiometer for the DAC you re ...

Page 35: ...t and subsequent board initializations 1 2 Gain Adjust 1 2 1 Apply a known voltage3 to the A D Input 1 2 2 Acquire the voltage using the A D converter 1 2 3 Adjust the value in the digital calibration potentiometer for the A D until the voltage read by the A D matches the input voltage 1 2 4 Store the value from the digital calibration potentiometer into a spot2 in the EEPROM for use on the next a...

Page 36: ...in x1 setting The software gain amplifier is a laser trimmed part and does not need separate calibration per setting For optimum results data should be heavily averaged to eliminate any noise from the computations 1 1 3 Adjust the value in the digital calibration potentiometer for the A D until the voltage read by the A D indicates 1 count Many methods of determining values for the digital calibra...

Page 37: ...g If the result is off scale reading 0000 or FFFF counts set the Pot to FF and take another reading One of these two readings will not be railed off scale Increment or decrement the Pot load value until the data read from the A D reads the Known Voltage To convert from counts to voltage use the following equation Volts Span Counts MaxCounts Offset MaxCounts on a 16 bit A D is 65536 and Span and Of...

Page 38: ...s as read with the Table B 1 and read the EEPROM entries for the A D Offset A D Gain and the DAC 0 and DAC 1 corrections Base 18 in Chapter 5 describes the process of reading from the EEPROM 2 3 Write each calibration constant to the correct Digital Calibration Potentiometer Refer to Chapter 5 Base 19 for more information on writing to the Digital Potentiometers EEPROM Location Calibration Value S...

Page 39: ...h this manual or just want to give us some feedback please email us at manuals accesio com Please detail any errors you find and include your mailing address so that we can send you any manual updates 10623 Roselle Street San Diego CA 92121 Tel 858 550 9559 FAX 858 550 7322 www accesio com ...

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