Manual 104-AIO16A and 104-AIO16E
8
A/D FIFO
The A/D FIFO buffers the data out of the ADC. This allows conversions to happen without constant CPU
intervention. Furthermore, the FIFO's half-full and full flags are readable by software. They can also be
used to generate interrupts. If the FIFO becomes full, A/D conversions are paused and resume when at
least one A/D sample is read out of the FIFO.
Interrupt Request (IRQ)
This board can be software enabled to generate an IRQ when the A/D FIFO becomes half-full or full. An
IRQ can also be generated after the end of a conversion (EOC) or after the end of a scan (EOS). These
IRQs help in taking A/D data off the board quickly.
The selection of the IRQ to be used is made by selecting one of the IRQ jumpers on the board. The
location of these jumpers is shown in the Option Selection Map.
Place a jumper on the posts corresponding to the IRQ you wish to select. If you do not intend on using
IRQs, do not install a jumper on any IRQ pins.
Analog Outputs (DAC)
There are two analog outputs on this board. Each analog output is adjusted by output calibration circuitry
including a digital potentiometer. The DACs have two output ranges of 0-5V or 0-10V. These are
individually chosen through jumper selections on the board. Refer to the option selection map for the
jumper selections. Please note that the DACs are labeled DAC A and DAC B on the PC board but
typically referred to as DAC 0 and DAC 1 in the manual. These terms are interchangeable as DAC 0 is
the same as DAC A, DAC 1 the same as DAC B.
The digital calibration potentiometers are serial devices, with data being entered bit by bit. Although the
details of writing bit by bit are described in Appendix B, it is expected that data will be loaded using a
software subroutine. Make sure that the correct calibration constants are loaded into the digital
potentiometers before using the analog outputs. Refer to Appendix B for calibrating the DACs.
Lastly, the DACs have a mode of operation called simultaneous update that will update both DACs
simultaneously after DAC1 has been written to. Otherwise, each DAC will update upon being written to.
Refer to Chapter 5: Programming for configuration details.
Digital I/O
This board contains an 8255 like Programmable Peripheral Interface (PPI). There are 2 ports, A and B,
available for Digital I/O. Both the low byte (port A) and high byte (port B) can be individually software
configured as inputs or outputs. In output mode, each port supports readback of the last written values.
Each DIO line is capable of sourcing 24mA or sinking 24mA. By default the DIO lines are pulled up with a
10k
Ω
resistor to 5V.
Counter/Timer
The highly versatile 8254 contains three counter/timers. Counter/Timer 0 is available for general purpose
use. Counter/Timer 1&2 are dedicated for use in timing A/D starts. The output of Counter/Timer 2 is
available on the P2 connector.
Counter/Timer 0’s clock and output signals are brought out to the connector. Both signals are buffered
and capable of sourcing 24mA or sinking 24mA. Counter/Timer 0’s clock is pulled up with a 10K
Ω
resistor to 5V.
Counter/Timer 0’s clock input is software selectable between an internal 10MHz clock and the external
Counter/Timer 0 clock on the P2 connector. The maximum allowed frequency for the clock is 10MHz.
