Abit KG7, User Manual

Page: 47 / 104

Introducing the BIOS
User’s Manual
3-19
"
SDRAM Idle Limit:
Eight options are available: 0 Cycle
)
8 Cycle
)
12 Cycle
)
16 Cycle
)
24 Cycle
)
32 Cycle
)
48 Cycle
)
Disabled
)
Back to 0 Cycle. The default setting is 8 Cycle. This is the number of idle
cycles to wait before recharging. Idle cycles are defined as cycles where no valid requests are sent to
the memory controller.
"
SDRAM Trc Timing Value:
Eight options are available: 3 Cycle
)
4 Cycle
)
5 Cycle
)
6 Cycle
)
7 Cycle
)
8 Cycle
)
9
Cycle
)
10 Cycle
)
Back to 3 Cycle. The default setting is 8 Cycle.
Trc timing value (Bank cycle time – minimum time from activate to activation of same bank).
"
SDRAM Trp Timing Value:
Four options are available: 3 Cycle
)
2 Cycle
)
1 Cycle
)
4 Cycle
)
Back to 3 Cycle. The
default setting is 3 Cycle.
Trp timing value (Precharge time – time from precharge command to when back can be activated).
"
SDRAM Tras Timing Value:
Eight options are available: 2 Cycle
)
3 Cycle
)
4 Cycle
)
5 Cycle
)
6 Cycle
)
7 Cycle
)
8
Cycle
)
9 Cycle
)
Back to 2 Cycle. The default setting is 7 Cycle.
Tras timing value = Minimum bank active time from activate to precharge of same bank.
"
SDRAM Trcd Timing Value:
Four options are available: 1 Cycle
)
2 Cycle
)
3 Cycle
)
4 Cycle
)
Back to 1 Cycle. The
default setting is 3 Cycle.
Trcd timing value = RAS to CAS latency + rd/wr command delay
"
Read Wait State:
Two options are available: 0 Cycle and 1 Cycle. The default setting is 1 Cycle . This item (bit)
determines whether a wait state must be added before returning the read data from the memory to the
requester. This bit should be programmed depending on the overall round-trip timing. Note that this
bit must
not be set if the DDR interface is clocked at 66MHz.
"
Write Data In to Delay:
Two options are available: 1 Cycle and 2 Cycle. The default setting is 2 Cycle . This item (bit) controls
the number of clock cycles that must occur between the last valid write operation and the next read
command. When you set it to “1 Cycle”, t
WTR
duration is 1 clock cycle, etc.
"
Write Recovery Time:
Three options are available: 1 Cycle, 2 Cycle and 3 Cycle. The default setting is 2 Cycle . This item
(bit) controls the number of clock cycles that must occur from the last valid write operation to the
earlist time a new Precharge command can be asserted to the same bank. When you set it to “1 Cycle”,
t
WTR
duration is 1 clock cycle, etc.
"
Act Bank A To B CMD Delay (Active Bank A to Active Bank B Command Delay):
Two options are available: 2 Cycle and 3 Cycle. The default setting is 2 Cycle . This item (bit) controls
the number of clock cycle between successive ACTIVE commands to different banks. When you set
it to “3 Cycle”, t
RRD
duration is 3 clock cycles, etc.