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UM031 FMC168/4/2

r1.7

UM031

page 24 of 28

AV57.1

LPC Pin Signal

AV57.1

HPC Pin Signal

AV57.1

HPC Pin Signal

LA18_P_CC

C22

CHE_D10_P

HA22_P

J21

CHG_D12_P

LA19_N

H23

CHE_D2_N

HA23_N

K23

CHG_D14_N

GBTCLK1_M2C_N

B21

GBTCLK1_N

LA19_P

H22

CHE_D2_P

HA23_P

K22

CHG_D14_P

GBTCLK1_M2C_P

B20

GBTCLK1_P

LA20_N

G22

CHE_D8_N

LA20_P

G21

CHE_D8_P

LA21_N

H26

CHG_D10_N

LA21_P

H25

CHG_D10_P

LA22_N

G25

CHE_D4_N

DP1_C2M_N

A23

DP_C2M_N<1>

LA22_P

G24

CHE_D4_P

DP1_C2M_P

A22

DP_C2M_P<1>

LA23_N

D24

CHG_D2_N

DP1_M2C_N

A3

DP_M2C_N<1>

LA23_P

D23

CHG_D2_P

DP1_M2C_P

A2

DP_M2C_P<1>

LA24_N

H29

CHF_D2_N

DP2_C2M_N

A27

DP_C2M_N<2>

LA24_P

H28

CHF_D2_P

DP2_C2M_P

A26

DP_C2M_P<2>

LA25_N

G28

CHG_D8_N

DP2_M2C_N

A7

DP_M2C_N<2>

LA25_P

G27

CHG_D8_P

DP2_M2C_P

A6

DP_M2C_P<2>

LA26_N

D27

CHG_D4_N

DP3_C2M_N

A31

DP_C2M_N<3>

LA26_P

D26

CHG_D4_P

DP3_C2M_P

A30

DP_C2M_P<3>

LA27_N

C27

CHF_D4_N

DP3_M2C_N

A11

DP_M2C_N<3>

LA27_P

C26

CHF_D4_P

DP3_M2C_P

A10

DP_M2C_P<3>

LA28_N

H32

CHF_D8_N

DP4_C2M_N

A35

DP_C2M_N<4>

LA28_P

H31

CHF_D8_P

DP4_C2M_P

A34

DP_C2M_P<4>

LA29_N

G31

CHF_D10_N

DP4_M2C_N

A15

DP_M2C_N<4>

LA29_P

G30

CHF_D10_P

DP4_M2C_P

A14

DP_M2C_P<4>

LA30_N

H35

CHH_D10_N

DP5_C2M_N

A39

DP_C2M_N<5>

LA30_P

H34

CHH_D10_P

DP5_C2M_P

A38

DP_C2M_P<5>

LA31_N

G34

CHH_D4_N

DP5_M2C_N

A19

DP_M2C_N<5>

LA31_P

G33

CHH_D4_P

DP5_M2C_P

A18

DP_M2C_P<5>

LA32_N

H38

CHH_D8_N

DP6_C2M_N

B37

DP_C2M_N<6>

LA32_P

H37

CHH_D8_P

DP6_C2M_P

B36

DP_C2M_P<6>

LA33_N

G37

CHH_D2_N

DP6_M2C_N

B17

DP_M2C_N<6>

LA33_P

G36

CHH_D2_P

DP6_M2C_P

B16

DP_M2C_P<6>

DP7_C2M_N

B33

DP_C2M_N<7>

DP7_C2M_P

B32

DP_C2M_P<7>

DP7_M2C_N

B13

DP_M2C_N<7>

GBTCLK0_M2C_

N

D5

GBTCLK0_N

CLK_DIR

B1

‘1’

DP7_M2C_P

B12

DP_M2C_P<7>

GBTCLK0_M2C_P

D4

GBTCLK0_P

PG_C2M

D1

PG_C2M

DP8_C2M_N

B29

DP_C2M_N<8>

DP0_C2M_N

C3

DP_C2M_N<0>

DP8_C2M_P

B28

DP_C2M_P<8>

DP0_C2M_P

C2

DP_C2M_P<0>

DP8_M2C_N

B9

DP_M2C_N<8>

DP0_M2C_N

C7

DP_M2C_N<0>

DP8_M2C_P

B8

DP_M2C_P<8>

DP0_M2C_P

C6

DP_M2C_P<0>

DP9_C2M_N

B25

DP_C2M_N<9>

PG_M2C

F1

PG_M2C

DP9_C2M_P

B24

DP_C2M_P<9>

I2C_SCL

C30

I2C_SCL

DP9_M2C_N

B5

DP_M2C_N<9>

I2C_SDA

C31

I2C_SDA

DP9_M2C_P

B4

DP_M2C_P<9>

Table 12: FMC168/4/2 - DDR MODE (yellow cells are N.C. on FMC164 and FMC162, blue

cells are N.C. on FMC162)

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Summary of Contents for FMC162

Page 1: ... 1 of 28 FMC168 4 2 User Manual FMC168 FMC164 FMC162 Abaco Systems Support Portal This document is the property of Abaco Systems and may not be copied nor communicated to a third party without the written permission Abaco Systems Abaco Systems 2017 ...

Page 2: ... FMC162 2 channel variant 2014 03 18 1 3 Revised some descriptions and fixed typos 2014 04 07 1 4 Correction in main characteristics table Corrected I2C and CPLD information 2014 06 17 1 5 Corrected external VCO part number 2014 09 08 1 6 Removed reference to cutoff filter in section 2015 03 06 1 7 Update to the Abaco format Added description about heatsink option in the cooling section EBa JHN JD...

Page 3: ... 2 4 Stacked FMC 9 4 2 5 JTAG 10 4 3 Main characteristics 10 4 4 Analog input channels 11 4 4 1 AC coupling 11 4 4 2 DC coupling 11 4 5 External clock input 12 4 6 External clock output 12 4 7 External trigger sync input 12 4 8 Clock tree 12 4 8 1 Architecture 12 4 8 2 PLL design 14 4 9 Power supply 14 5 Controlling the FMC168 4 2 14 5 1 CPLD 15 5 2 Onboard monitoring 16 6 Environment 16 6 1 Tempe...

Page 4: ...UM031 FMC168 4 2 r1 7 UM031 www abaco com page 4 of 28 Appendix B FMC168 4 2 connector pin out DDR mode 23 Appendix C CPLD Register map 27 ...

Page 5: ...gnificant Bit s LVDS Low Voltage Differential Signaling MGT Multi Gigabit Transceiver MSB Most Significant Bit s PCB Printed Circuit Board PCI Peripheral Component Interconnect PCIe PCI Express PLL Phase Locked Loop PMC PCI Mezzanine Card PSSR Power Supply Rejection Ratio QDR Quadruple Data rate SDRAM Synchronous Dynamic Random Access memory SRAM Synchronous Random Access memory TTL Transistor Log...

Page 6: ...pled or DC coupled connecting to SSMC coax connectors on the front panel In addition the FMC164 and FMC162 offer optional differential inputs The FMC168 4 2 allows flexible control of sampling frequency and analog input gain through the I2 C communication bus Furthermore the card is equipped with power supply and temperature monitoring and offers several power down modes to switch off unused funct...

Page 7: ... must support VIO_B equal to VADJ 4 Design 4 1 Physical specifications 4 1 1 Board Dimensions The FMC168 4 2 card complies with the FMC standard known as ANSI VITA 57 1 The card is a single width conduction cooled mezzanine module with region 1 and front panel I O Although the card has a front panel I O it is compatible with most fixed rib carrier cards The front area holds 10 SSMC connectors that...

Page 8: ...l names A Input 1st A D CHA_ B Input 2nd A D CHB_ C Input 3rd A D CHC_ D Input 4th A D CHD_ E Input 5th A D CHE_ F Input 6th A D CHF_ G Input 7th A D CHG_ H Input 8th A D CHH_ Table 2 FMC168 Connector function assignment FMC164 Single ended FMC164 Differential Font Label Input FMC connector signal names Font Label Input FMC connector signal names A Input 1st A D CHA_ A Non Inverted input 1st A D C...

Page 9: ...l uses four LVDS pairs at 500MHz DDR with a sampling frequency of 250MHz This mode can be used by both LPC and HPC carrier hardware 4 2 2 DDR LVDS mode In DDR LVDS mode each channel uses eight LVDS pairs at 250MHz DDR with a sampling frequency of 250MHz This mode can only be used by HPC carrier hardware 4 2 3 EEPROM The FMC168 4 2 card carries a serial EEPROM M24C02 WDW6 which is accessible from t...

Page 10: ...Contact Abaco for detailed information TDI TDO TDI TDO PRSNT_M2C_L PRSNT_M2C_L Top connector to FMC carrier Bottom connector to stacked FMC 3P3V OE TMS TMS TCK TCK TRST TRST CPLD Figure 5 JTAG connections 4 3 Main characteristics Analog inputs Number of channels 8 FMC168 4 FMC164 2 FMC162 Channel resolution 16 bit Input voltage range 1Vp p 4dBm to 2Vp p 10 dBm programmable Input gain Programmable ...

Page 11: ...istics 4 4 Analog input channels The analog input signals are connected to the FMC168 4 2 via SSMC connectors on the front panel Each channel can be assembled as an AC coupled or DC coupled input Optionally the FMC164 2 supports differential inputs using two connectors per channel A 125MHz low pass input filter can be assembled The filter option needs to be specified at the time of ordering See Ch...

Page 12: ...ill be a LVTTL output driven from the AD9517 It s a build option The trigger connector can be used as clock output Contact Abaco for details 4 7 External trigger sync input The external trigger input can be configured in different ways depending on the build option The trigger input can be 50Ω terminated accepting most common high speed signalling standards like single ended LVPECL By default the ...

Page 13: ... onboard oscillator is connected in parallel with the clock input behind the RF transformer To avoid interference there should be no signal applied to clock input when internal reference is used Figure 8 Clock tree The AD9517 outputs are allocated as follows OUT0 is an LVPECL output and is used for clocking the ADC devices through an ADCLK944 fan out buffer OUT 1 3 are unused and must be disabled ...

Page 14: ...C standard power specification The power provided by the carrier card can be very noisy Special care is taken with the power supply generation on the FMC168 4 2 card to minimize the effect of power supply noise on clock generation and data conversion However properly filtered power supplies from the FMC carrier are recommended Table 7 shows typical currents per power rail VIO_B is connected to VAD...

Page 15: ...VITA 57 1 the least significant address bit of the EEPROM connects to GA1 EEPROM address bit 1 connects to GA0 5 1 CPLD The FMC168 4 2 has an onboard CPLD XC2C256 CP132 used to control different devices on board The CPLD communicates with the carrier hardware via an I2 C interface and acts as an I2 C to SPI bridge Refer to the Appendix for register and control details 3 3V BANK ADG3304 VADJ 3 3V 4...

Page 16: ...ernal AIN5 3 3V Analog Clock AIN5 2 External AIN6 VCP AIN6 3 128 External AIN7 1 8V Analog Clock AIN7 1 Table 9 Temperature and voltage parameters 6 Environment 6 1 Temperature Operating temperature 0 C to 70 C Commercial 40 C to 85 C Industrial Storage temperature 40 C to 120 C 6 2 Monitoring One AD7291 device may be used to monitor the voltage on the different power rails and the environment tem...

Page 17: ...might be sufficient to maintain the temperature within operating boundaries some active cooling would yield better results and would certainly help with resuming operations much faster if the devices are disabled because of a temperature over range 7 Safety This module presents no hazard to the user Supplies used to power the FMC module shall not exceed the voltage and current limits as specified ...

Page 18: ...UM031 FMC168 4 2 r1 7 UM031 www abaco com page 18 of 28 optional ...

Page 19: ...HA09_N E10 CHC_CLK_N HB09_N E28 N C LA05_P D11 CHA_D1_P HA09_P E9 CHC_CLK_P HB09_P E27 N C LA06_N C11 CHC_D3_N HA10_N K14 CHB_FRM_N HB10_N K32 FMC_TO_CPLD1 LA06_P C10 CHC_D3_P HA10_P K13 CHB_FRM_P HB10_P K31 FMC_TO_CPLD0 LA07_N H14 CHC_D2_N HA11_N J13 CHB_OVR HB11_N J31 FMC_TO_CPLD3 LA07_P H13 CHC_D2_P HA11_P J12 N C HB11_P J30 FMC_TO_CPLD2 LA08_N G13 CHC_D1_N HA12_N F14 N C HB12_N F32 N C LA08_P ...

Page 20: ... DP_C2M_N 4 LA28_P H31 CHF_D2_P DP4_C2M_P A34 DP_C2M_P 4 LA29_N G31 CHF_D3_N DP4_M2C_N A15 DP_M2C_N 4 LA29_P G30 CHF_D3_P DP4_M2C_P A14 DP_M2C_P 4 LA30_N H35 CHH_D0_N DP5_C2M_N A39 DP_C2M_N 5 LA30_P H34 CHH_D0_P DP5_C2M_P A38 DP_C2M_P 5 LA31_N G34 CHH_D2_N DP5_M2C_N A19 DP_M2C_N 5 LA31_P G33 CHH_D2_P DP5_M2C_P A18 DP_M2C_P 5 LA32_N H38 CHH_D1_N DP6_C2M_N B37 DP_C2M_N 6 LA32_P H37 CHH_D1_P DP6_C2M_...

Page 21: ... channel E F G H Not connected on FMC162 CHE_D 3 0 _P N A D N C on FMC162 Output LVDS A D data output channel E Not connected on FMC162 CHF_D 3 0 _P N A D N C on FMC164 2 Output LVDS A D data output channel F Not connected on FMC164 2 CHG_D 3 0 _P N A D N C on FMC162 Output LVDS A D data output channel G Not connected on FMC162 CHH_D 3 0 _P N A D N C on FMC164 2 Output LVDS A D data output channel...

Page 22: ...K_DIR is pulled to 3V3 with 10kOhm The direction of CLK2 is from Module to Carrier CLK3 is unused FMC_TO_CPLD 3 0 CONTROL Bidir VADJ Reserved for future use GBTCLK0_M2C_P N MGT N A N A Refer to section 4 2 2 GBTCLK1_M2C_P N MGT N A N A Refer to section 4 2 2 DP 0 9 _C2M_P N MGT N A N A Refer to section 4 2 2 DP 0 9 _M2C_P N MGT N A N A Refer to section 4 2 2 Table 11 Signal description FMC168 4 2 ...

Page 23: ...A05_N D12 CHA_D4_N HA09_N E10 CHC_D6_N HB09_N E28 CHH_D12_N LA05_P D11 CHA_D4_P HA09_P E9 CHC_D6_P HB09_P E27 CHH_D12_P LA06_N C11 CHC_D2_N HA10_N K14 CHB_D12_N HB10_N K32 FMC_TO_CPLD1 LA06_P C10 CHC_D2_P HA10_P K13 CHB_D12_P HB10_P K31 FMC_TO_CPLD0 LA07_N H14 CHC_D4_N HA11_N J13 CHB_D14_N HB11_N J31 FMC_TO_CPLD3 LA07_P H13 CHC_D4_P HA11_P J12 CHB_D14_P HB11_P J30 FMC_TO_CPLD2 LA08_N G13 CHC_D8_N ...

Page 24: ...M_N A35 DP_C2M_N 4 LA28_P H31 CHF_D8_P DP4_C2M_P A34 DP_C2M_P 4 LA29_N G31 CHF_D10_N DP4_M2C_N A15 DP_M2C_N 4 LA29_P G30 CHF_D10_P DP4_M2C_P A14 DP_M2C_P 4 LA30_N H35 CHH_D10_N DP5_C2M_N A39 DP_C2M_N 5 LA30_P H34 CHH_D10_P DP5_C2M_P A38 DP_C2M_P 5 LA31_N G34 CHH_D4_N DP5_M2C_N A19 DP_M2C_N 5 LA31_P G33 CHH_D4_P DP5_M2C_P A18 DP_M2C_P 5 LA32_N H38 CHH_D8_N DP6_C2M_N B37 DP_C2M_N 6 LA32_P H37 CHH_D8...

Page 25: ...Not connected on FMC164 2 CHEG_CLK_P N A D N C on FMC162 Output LVDS Clock for capturing A D data outputs of channel E and G Not connected on FMC162 CHE_D 14 2 0 _P N A D N C on FMC162 Output LVDS A D data output channel E Not connected on FMC162 CHG_D 14 2 0 _P N A D N C on FMC162 Output LVDS A D data output channel G Not connected on FMC162 CHFH_CLK_P N A D N C on FMC164 2 Output LVDS Clock for ...

Page 26: ... of 28 Signal Group Direction I O Std Description GBTCLK1_M2C_P N MGT N A N A Refer to section 4 2 2 DP 0 9 _C2M_P N MGT N A N A Refer to section 4 2 2 DP 0 9 _M2C_P N MGT N A N A Refer to section 4 2 2 Table 13 Signal description FMC168 4 2 DDR mode ...

Page 27: ...0 Bit 1 Always 0 Bit 2 Level of STATUS output from AD9517 Bit 3 Level of REFMON output from AD9517 Bit 4 Level of LD output from AD9517 Bit 5 Always 0 Bit 6 Always 0 Bit 7 Level of ALERT output from AD7291 0x03 Version register Read only Bit 7 0 0x2A initial release with basic functions SPI readback from ADC devices is not available Command register not available Two LSB of I2C address fixed to 00...

Page 28: ...ADS42LB69 1 Channel B and D x 10 for selecting ADS42LB69 2 Channel E and G x 20 for selecting ADS42LB69 3 Channel F and H x 3C for selecting all ADS42LB69 Note for CPLD version 0x2A it is required to set bit 1 for AD9517 communication and bit 6 for ADC communication It is recommended to upgrade the CPLD to a newer version Contact Abaco technical support 0x0F SPI Data read back Read only Table 14 C...

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