UM031 FMC168/4/2
r1.7
UM031
page 21 of 28
Signal
Group
Direction
I/O Std
Description
CLK_TO_FPGA_P/N
STATUS
Output
LVDS
Spare clock output from AD9517
(OUT6). May be used for
monitoring.
EXT_TRIGGER_P/N
TRIGGER
Output
LVDS
Representation of the signal
connected to the external trigger
input.
SYNC_FROM_FPGA_P/N
SYNC
Input
LVDS
This is an optional signal that may
be used to drive the
synchronisation logic.
CHA_CLK_P/N
A/D
Output
LVDS
Clock for capturing A/D data
outputs of channel A, B,C,D.
CHA_D<3..0>_P/N
A/D
Output
LVDS
A/D data output channel A.
CHB_D<3..0>_P/N
A/D
(N.C. on FMC164/2)
Output
LVDS
A/D data output channel B.
Not connected on FMC164/2.
CHC_D<3..0>_P/N
A/D
Output
LVDS
A/D data output channel C.
CHD_D<3..0>_P/N
A/D
(N.C. on FMC164/2)
Output
LVDS
A/D data output channel D.
Not connected on FMC164/2.
CHE_CLK_P/N
A/D
(N.C. on FMC162)
Output
LVDS
Clock for capturing A/D data
outputs of channel E, F,G,H.
Not connected on FMC162.
CHE_D<3..0>_P/N
A/D
(N.C. on FMC162)
Output
LVDS
A/D data output channel E.
Not connected on FMC162.
CHF_D<3..0>_P/N
A/D
(N.C. on FMC164/2)
Output
LVDS
A/D data output channel F.
Not connected on FMC164/2.
CHG_D<3..0>_P/N
A/D
(N.C. on FMC162)
Output
LVDS
A/D data output channel G.
Not connected on FMC162.
CHH_D<3..0>_P/N
A/D
(N.C. on FMC164/2)
Output
LVDS
A/D data output channel H.
Not connected on FMC164/2.
CH<A..H>_OVR
OPTIONAL
Output
LVCMOS18
Over-range signal per channel.
Refer to ADS42LB69. Abaco
reference design is not using the
over-range signals to support LPC
applications.
CH<A..H>_FRM_P/N
OPTIONAL
Output
LVDS
Frame signal per channel. Refer to
ADS42LB69. Abaco reference
design is not using the frame
signal to support LPC applications.
CH<B..D>_CLK_P/N
CH<F..H>_CLK_P/N
OPTIONAL
Output
LVDS
Clock signal per channel. Refer to
ADS42LB69. Abaco reference
design is only using
CHA_CLK_P/N and
CHE_CLK_P/N to support LPC
applications.
PG_C2M
STATUS
Input
LVTTL
Power good indicator from carrier
to module
PG_M2C
STATUS
Output
LVTTL
Power good indicator from module
to carrier
