abaco systems FMC162, User Manual, Page: 12 / 28

UM031 FMC168/4/2 r1.7
UM031 www.abaco.com page 12 of 28
coupled applications, there is a provision for an optional 5
th
order low-pass. The filter design
can be specified at the time of ordering. Please contact your sales channel for more details.
4.5 External clock input
There is one clock input on the front panel that can serve as sampling clock input or as
reference clock input if the internal clock is desired. Refer also to Chapter 4.8 for more
information about the clock tree.
Note 1: When internal clock is enabled and there is no need for an external reference,
it is highly recommended to leave the clock input unconnected to prevent interference
with the internal clock.
Note 2: When external clock is enabled, the onboard VCO might cause interference.
The VCO cannot be powered down on the FMC168/4 r1.0. Please contact Abaco to
have the onboard VCO disabled for external clock applications.
4.6 External clock output
The external clock output will be a LVTTL output driven from the AD9517. It’s a build option.
The trigger connector can be used as clock output. Contact Abaco for details.
4.7 External trigger/sync input
The external trigger input can be configured in different ways depending on the build option.
The trigger input can be 50
Ω
terminated, accepting most common high-speed signalling
standards like single-ended LVPECL. By default, the 50
Ω termination is not mo
unted in order
to support LVTTL/LVCMOS and similar input standards. By default, the input is single-ended
and DC-
coupled with an input impedance of approximately 2.5kΩ. The input threshold is
approximately 1.25V.
Optionally, the trigger input can be used as sync input, synchronizing local A/D converters or
multiple cards.
TRIGGER
Any Level
to LVDS
1:2 Fanout
SYNC_FROM_CPLD_P/N
Fs/4 from Clock Tree
LVDS
MUX
to FMC
SYNCSRC_SEL[1:0]
S SYNC_FROM_FPGA_P/N
ADC#1
ADC#2
ADC#3
ADC#4
ADCLK
944
Figure 7: A/D Synchronization topology
4.8 Clock tree
4.8.1 Architecture
The FMC168/4/2 card offers a clock architecture that combines flexibility and high
performance. Components have been chosen in order to minimize jitter and phase noise to