Auto
Pre-defined values for DRAM, cache..timing
Configuration
according to CPU type & system clock.
When this item is enabled, the pre-defined
items will become SHOW-ONLY.
DRAM Timing
The DRAM speed is controlled by the DRAM
timing Registers. The timings programmed
into this register are dependent on the
system design.
Fast RAS# to
When DRAM is refreshed, both rows and
CAS# Delay
columns are addressed separately. This
setup item allows you to determine the
timing of the transition from RAS to Column
Address Strobe (CAS).
DRAM Read
This sets the timing for burst mode read (or
Burst (EDO/FP)
writes)from DRAM. Burst read and write
DRAM Write
requests are generated by the CPU in four
Burst Timing
separate parts. The first part provides the
location within the DRAM where the read or
write is to take place while the remaining
three parts provide the actual data. The
lower the timing numbers, the faster the
system will address memory.
System BIOS
When enabled, accesses to the system BIOS
Cacheable
ROM addressed at F0000H-FFFFFH are
cached, provided that the cache controller
is enabled.
Video BIOS
As with changing the system BIOS above,
Cacheable
enabling the Video BIOS cache will cause
access to video BIOS addressed at C0000H
to C7FFFH to be cached, if the cache
controller is also enabled.
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Summary of Contents for ATC-5030
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