UM012811-0904
Opcodes Listed Numerically
eZ8 CPU
User Manual
205
20
INC dst
R
-
*
*
*
-
-
2
2
21
INC dst
IR
-
*
*
*
-
-
2
3
22
SUB dst, src
r
r
*
*
*
*
1
*
2
3
23
SUB dst, src
r
Ir
*
*
*
*
1
*
2
4
24
SUB dst, src
R
R
*
*
*
*
1
*
3
3
25
SUB dst, src
R
IR
*
*
*
*
1
*
3
4
26
SUB dst, src
R
IM
*
*
*
*
1
*
3
3
27
SUB dst, src
IR
IM
*
*
*
*
1
*
3
4
28
SUBX dst, src
ER
ER
*
*
*
*
1
*
4
3
29
SUBX dst, src
ER
IM
*
*
*
*
1
*
4
3
2A
DJNZ dst, RA
r
-
-
-
-
-
-
2
3
2B
JR LE, dst
DA
-
-
-
-
-
-
2
2
2C
LD dst, src
r
IM
-
-
-
-
-
-
2
2
2D
JP LE, dst
DA
-
-
-
-
-
-
3
2
2E
INC dst
r
-
*
*
*
-
-
1
2
2F
ATM
-
-
-
-
-
-
1
2
30
DEC dst
R
-
*
*
*
-
-
2
2
31
DEC dst
IR
-
*
*
*
-
-
2
3
32
SBC dst, src
r
r
*
*
*
*
1
*
2
3
33
SBC dst, src
r
Ir
*
*
*
*
1
*
2
4
34
SBC dst, src
R
R
*
*
*
*
1
*
3
3
35
SBC dst, src
R
IR
*
*
*
*
1
*
3
4
36
SBC dst, src
R
IM
*
*
*
*
1
*
3
3
37
SBC dst, src
IR
IM
*
*
*
*
1
*
3
4
38
SBCX dst, src
ER
ER
*
*
*
*
1
*
4
3
39
SBCX dst, src
ER
IM
*
*
*
*
1
*
4
3
Table 23. eZ8 CPU Instructions Sorted by Opcode
Opcode(s)
(Hex)
Assembly Mnemonic
Address Mode
Flags
Fetch
Cycles
Instr.
Cycles
dst
src
C
Z
S
V
D
H
Flags Notation: * = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1