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6. DMA Controller
ÛZIATECH
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DMA Slave Operation
1. The DMA slave generates an STD bus BUSRQ* or a frontplane DMA request.
2. The system controller gains control of STD bus resources (multiple master only).
The system controller is hardware local to the ZT 8907 that manages the STD bus
interface.
3. The system controller generates a DMA request to the DMA controller if the
Bus
Own
bit (bit 5 of System Register 3 (E5h)) is active. In a single master system, this
bit is held active. In a multiple master system, this bit is software controlled to direct
the DMA request to a single destination.
4. The DMA controller (programmed to perform a DMA transfer) gains control of local
resources and generates a DMA acknowledge to the system controller.
5. The system controller generates an STD bus BUSAK* or a frontplane DMA
acknowledge.
6. The DMA controller generates an STD bus or frontplane I/O strobe and a local
memory cycle to complete the data transfer.