9-20
IM 704420-01E
Test method
• Test the TA120E after 30 minutes of warm-up.
• Set the slope and the phase difference of the TA120E signal to the values
indicated in the table below and confirm that the standard deviation
σ
(jitter) under
the D-to-C jitter measurement of the TA120E is within the allowable range in the
table.
Test procedure
1.
Set the output level of the 8657B to 720 mVrms and the frequency to 20 MHz.
2.
Set the slope of the data signal of the TA120E to
, the slope of the clock
signal to
, and the phase difference to [5.0ns].
3.
Read the standard deviation
σ
. Confirm that the value is within the allowable
range.
4.
Set the slope of the data signal of the TA120E, the slope of the clock signal, and
the phase difference according to the table below, then perform the test in a
similar fashion.
Test result
• Slope of the data signal:
, slope of the clock signal:
Phase difference between the data signal and
Standard Deviation
σ
(Jitter)
the clock signal
Measured Value
Allowable Range
5.0 ns
0.4 ns or less
10.0 ns
0.4 ns or less
30.0 ns
0.4 ns or less
• Slope of the data signal:
, slope of the clock signal:
Phase difference between the data signal and
Standard Deviation
σ
(Jitter)
the clock signal
Measured Value
Allowable Range
5.0 ns
0.4 ns or less
10.0 ns
0.4 ns or less
30.0 ns
0.4 ns or less
• Slope of the data signal:
, slope of the clock signal:
Phase difference between the data signal and
Standard Deviation
σ
(Jitter)
the clock signal
Measured Value
Allowable Range
5.0 ns
0.4 ns or less
10.0 ns
0.4 ns or less
30.0 ns
0.4 ns or less
• Slope of the data signal:
, slope of the clock signal:
Phase difference between the data signal and
Standard Deviation
σ
(Jitter)
the clock signal
Measured Value
Allowable Range
5.0 ns
0.4 ns or less
10.0 ns
0.4 ns or less
30.0 ns
0.4 ns or less
9.6 Executing the Performance Test