8-37
IM 704420-01E
Communication Function
8
Summary of the Registers and Queues
Name (Function)
Write
Read
Status byte
—
Serial polling
(
RQS
)
,
*STB?(MSS)
Service request
*SRE
*SRE?
enable register
(Status byte mask)
Standard event register
—
*ESR?
(Changes in device status)
Standard event
*ESE
*ESE?
enable register
(Standard event register mask)
Extended event register
—
STATus:EESR?
(Changes in device status)
Extended event
STATus:EESE
STATus:EESE?
enable register
(Extended event register mask)
Condition register
—
STATus:CONDition?
(Current device status)
Transition filter
STATus:FILTer<x> STATus:FILTer<x>?
(Conditions that change the extended event register)
Output queue
All query commands
(Stores a response message to a query)
Error queue
—
STATus:ERRor?
(Stores the error No. and message)
Registers and Queues That Affect the
Status Byte
Registers that affect the bits of the status byte are
shown below.
• Standard event register: Sets bit 5 (ESB) of the status byte to “
1
”
or “
0
.”
• Output queue: Sets bit 4 (MAV) of the status byte to “
1
” or “
0
.”
• Extended event register: Sets bit 3 (EES) of the status byte to “
1
”
or “
0
.”
• Error queue: Sets bit 2 (EAV) of the status byte to “
1
” or “
0
.”
Enable Registers
Registers that are used to mask a bit so that the bit will
not affect the status byte, even if it is set to
1
, are
shown below.
• Status byte: Mask the bits using the service request enable
register.
• Standard event register: Mask the bits using the standard event
enable register.
• Extended event register: Mask the bits using the extended event
enable register.
Reading and Writing to the Registers
For example, the
*ESE
command is used to set the bits
in the standard event register to
1
s or
0
s. The
*ESE?
command is used to query whether the bits in the
standard event register are
1
s or
0
s. For details
regarding these commands, see section 8.7.
8.8.2 Status Byte
Status Byte
7
6
ESB MAV EES EAV
1
0
RQS
MSS
Bits 0, 1, and 7
Not used (always 0)
Bit 2
EAV (Error Available)
Set to “
1
” when the error queue is not empty. In
other words, this bit is set to “
1
” when an error
occurs. See the page 8-40.
Bit 3
EES (Extend Event Summary Bit)
Set to “
1
” when the logical product of the extended
event register and the corresponding event register
is “
1
.” In other words, this bit is set to “
1
” when an
event occurs inside the instrument. See the page 8-
39.
Bit 4
MAV (Message Available)
Set to “
1
” when the output queue is not empty. In
other words, this bit is set to “
1
” when there are data
to be transmitted. See the page 8-40.
Bit 5
ESB (Event Summary Bit)
Set to “
1
” when the logical product of the standard
event register and the corresponding event register
is “
1
.” In other words, this bit is set to “
1
” when an
event occurs inside the instrument. See the page 8-
38.
Bit 6
RQS (Request Service)/MSS (Master
Status Summary)
Set to “
1
” when the logical AND of the status byte
excluding Bit 6 and the service request enable
register is not “
0
.” In other words, this bit is set to
“
1
” when the instrument is requesting service from
the controller.
RQS is set to “
1
” when the MSS bit changes from
“
0
” to “
1
,” and cleared when serial polling is carried
out or when the MSS bit changes to “
0
.”
Bit Masking
If you wish to mask a certain bit of the status byte so
that it does not cause an SRQ, set the corresponding
bit of the service request enable register to “
0
.”
For example, to mask bit 2 (EAV) so that service is not
requested when an error occurs, set bit 2 of the service
request enable register to “
0
.” This is done using the
*SRE
command. The
*SRE?
request command can be
used to query the service request enable register to
check whether each bit is set to “
1
” or “
0
.” For details
on the
*SRE
command, see section 8.7.
8.8 Status Report