Yamaha TF5, Руководство по обслуживанию

Страница: 92 / 372

92
TF5/TF3/TF1
MAIN (MAINCOM): IC905
PIN
NO. Outer
No
Name I/O Function
1 A1 VSS GND GND
2 A2 VDD_MPU_MON I Voltage Monitor Input(Not Used)
3 A3 RESERVED O Not Used
4 A4 OSC1_OUT O OSC1(for Internal RTC) Output
5 A5 VSS_RTC GND GND
6 A6 OSC1_IN I OSC1(for Internal RTC) Input
7 A7 AIN3 I A/D Input
8 A8 AIN6 I A/D Input
9 A9 VREFN I Analog Negative Reference Input
10 A10 NRESETIN_OUT BIDIRECT Active low Warm Reset
11 A11 TDO O JTAG TEST DATA OUTPUT
12 A12 TCK I JTAG TEST CLOCK
13 A13 SPI1_SCLK BIDIRECT SPI Clock
14 A14 GPIO3[21] BIDIRECT GPIO
15 A15 SPI1_CS1 BIDIRECT SPI Chip Select
16 A16 SPI0_CS0 BIDIRECT SPI Chip Select
17 A17 SPI0_SCLK BIDIRECT SPI Clock
18 A18 VSS GND GND
19 B1 DDR_A5 O DDR SDRAM ROW/COLUMN ADDRESS Output
20 B2 DDR_WEN O DDR SDRAM WRITE ENABLE OUTPUT (ACTIVE LOW)
21 B3 DDR_BA2 O DDR SDRAM BANK ADDRESS OUTPUT
22 B4 ENZ_KALDO_1P8V I Active low enable input for internal CAP_VDD_RTC voltage regulator
23 B5 RTC_PORZ I Active low RTC reset input
24 B6 AIN0 I A/D Input
25 B7 AIN2 I A/D Input
26 B8 AIN5 I A/D Input
27 B9 VREFP I Analog Positive Reference Input
28 B10 NTRST I JTAG TEST RESET (ACTIVE LOW)
29 B11 TDI I JTAG TEST DATA INPUT
30 B12 GPIO3[18] BIDIRECT GPIO
31 B13 SPI1_D0 BIDIRECT SPI Data
32 B14 EMU1 BIDIRECT MISC EMULATION PIN
33 B15 PWRONRSTn I Active low Power on Reset
34 B16 SPI0_D1 BIDIRECT SPI Data
35 B17 SPI0_D0 BIDIRECT SPI Data
36 B18 NNMI I External Interrupt to ARM Cortext A8 core
37 C1 DDR_A9 O DDR SDRAM ROW/COLUMN ADDRESS Output
38 C2 DDR_A4 O DDR SDRAM ROW/COLUMN ADDRESS Output
39 C3 DDR_A3 O DDR SDRAM ROW/COLUMN ADDRESS Output
40 C4 DDR_BA0 O DDR SDRAM BANK ADDRESS OUTPUT
41 C5 EXT_WAKEUP I EXT_WAKEUP input
42 C6 PMIC_POWER_EN O PMIC_POWER_EN output(Not Used)
43 C7 AIN1 I A/D Input
44 C8 AIN4 I A/D Input
45 C9 AIN7 I A/D Input
46 C10 CAP_VBB_MPU VCC Cap for MPU Regulator
47 C11 TMS I JTAG TEST MODE SELECT
48 C12 GPIO3[17] BIDIRECT GPIO
49 C13 GPIO3[19] BIDIRECT GPIO
50 C14 EMU0 BIDIRECT MISC EMULATION PIN
51 C15 SPI0_CS1 BIDIRECT SPI Chip Select
52 C16 I2C0_SCL BIDIRECT I2C Clock
53 C17 I2C0_SDA BIDIRECT I2C0 Data
54 C18 GPIO0[7]
BIDIRECT GPIO
55 D1 DDR_NCK O DDR SDRAM CLOCK OUTPUT (Differential-)
56 D2 DDR_CK O DDR SDRAM CLOCK OUTPUT (Diffe)
57 D3 DDR_A15 O DDR SDRAM ROW/COLUMN ADDRESS Output
58 D4 DDR_A8 O DDR SDRAM ROW/COLUMN ADDRESS Output
59 D5 DDR_A6 O DDR SDRAM ROW/COLUMN ADDRESS Output
60 D6 CAP_VDD_RTC VCC Cap for RTC
61 D7 VDDS_RTC VCC VDDS for RTC
62 D8 VDDA_ADC VCC VDDA for ADC
63 D9 CAP_VDD_SRAM_CORE VCC Cap for SRAM Core VDD
64 D10 VDDS_SRAM_MPU_BB VCC VDDS for SRAM
65
D11 CAP_VDD_SRAM_MPU VCC Cap for VDD_SRAM_MPU
66 D12 SPI1_D1 BIDIRECT SPI Data
67 D13 GPIO3[20] BIDIRECT GPIO
68 D14 GPIO0[20] BIDIRECT GPIO
69 D15 UART1_TXD BIDIRECT UART Transmit Data
70 D16 UART1_RXD BIDIRECT UART Receive Data
71 D17 I2C2_SCL
BIDIRECT I2C Clock
72 D18 I2C2_SDA BIDIRECT I2C0 Data
73 E1 DDR_BA1 O DDR SDRAM BANK ADDRESS OUTPUT
74 E2 DDR_A7 O DDR SDRAM ROW/COLUMN ADDRESS Output
75 E3 DDR_A12 O DDR SDRAM ROW/COLUMN ADDRESS Output
76 E4 DDR_A2 O DDR SDRAM ROW/COLUMN ADDRESS Output
77 E5 VDDS_DDR VCC VDDS for DDR
78 E6 VDDS VCC VDDS
79 E7 VDDS_PLL_DDR VCC VDDS for DDR PLL
80 E8 VSSA_ADC GND GND(for ADC)
81 E9 VDDS_SRAM_CORE_BG VCC VDDS for SRAM Core
PIN
NO. Outer
No
Name I/O Function
82 E10 VDDSHV6 VCC VDD for I/O
83 E11 VDDSHV6 VCC VDD for I/O
84 E12 VDDSHV6 VCC VDD for I/O
85 E13 VDDSHV6 VCC VDD for I/O
86 E14 VDDS VCC VDDS
87 E15 UART0_RXD BIDIRECT UART Receive Data
88 E16 UART0_TXD BIDIRECT UART Transmit Data
89 E17 I2C1_SCL BIDIRECT I2C Clock
90 E18 I2C1_SDA BIDIRECT I2C0 Data
91 F1 DDR_CASN O DDR SDRAM COLUMN ADDRESS STROBE OUTPUT (ACTIVE LOW)
92 F2 DDR_A11 O DDR SDRAM ROW/COLUMN ADDRESS Output
93 F3 DDR_A0 O DDR SDRAM ROW/COLUMN ADDRESS Output
94 F4 DDR_A10 O DDR SDRAM ROW/COLUMN ADDRESS Output
95 F5 VDDS_DDR VCC VDDS for DDR
96 F6 VDD_CORE VCC VDD for Core
97 F7 VDD_CORE VCC VDD for Core
98 F8 VSS GND GND
99 F9 VDDS VCC VDDS
100 F10 VDD_MPU VCC VDD for MPU
101 F11 VDD_MPU VCC VDD for MPU
102 F12 VDD_MPU VCC VDD for MPU
103 F13 VDD_MPU VCC VDD for MPU
104 F14 VDDSHV6 VCC VDD for I/O
105 F15 USB1_DRVBUS BIDIRECT USB1 DRVBUS
106 F16 USB0_DRVBUS BIDIRECT USB0 DRVBUS
107 F17 GPIO2[26]
BIDIRECT GPIO
108 F18 GPIO2[27] BIDIRECT GPIO
109 G1 DDR_ODT O ODT OUTPUT
110 G2 DDR_RESETN O R3/DDR3L RESET OUTPUT(Not Used)
111 G3 DDR_CKE O DDR SDRAM CLOCK ENABLE OUTPUT
112 G4 DDR_RASN O DDR SDRAM ROW ADDRESS STROBE OUTPUT (ACTIVE LOW)
113 G5 VDDS_DDR VCC VDDS for DDR
114 G6 VDD_CORE VCC VDD for Core
115 G7 VDD_CORE VCC VDD for Core
116 G8 VSS GND GND
117 G9 VSS GND GND
118 G10 VDD_CORE VCC VDD for Core
119 G11 VSS GND GND
120 G12 VSS GND GND
121 G13 VDD_MPU VCC VDD for MPU
122 G14 VDDSHV6 VCC VDD for I/O
123 G15 GPIO2[28] BIDIRECT GPIO
124 G16 GPIO2[29] BIDIRECT GPIO
125 G17 GPIO2[30] BIDIRECT GPIO
126 G18 GPIO2[31] BIDIRECT GPIO
127 H1 DDR_A1 O DDR SDRAM ROW/COLUMN ADDRESS Output
128 H2 DDR_CSN0 O DDR SDRAM CHIP SELECT OUTPUT
129 H3 DDR_A13 O DDR SDRAM ROW/COLUMN ADDRESS Output
130 H4 DDR_A14 O DDR SDRAM ROW/COLUMN ADDRESS Output
131 H5 VDDS_DDR VCC VDDS for DDR
132 H6 VSS GND GND
133 H7 VSS GND GND
134 H8 VSS GND GND
135 H9 VSS GND GND
136 H10 VSS GND GND
137 H11 VDD_CORE VCC VDD for Core
138 H12 VSS GND GND
139 H13 VDD_MPU VCC VDD for Core
140 H14 VDDSHV4 VCC VDD for I/O
141 H15 VDDS_PLL_MPU VCC VDDS for MPU PLL
142 H16 GPIO3[0]
BIDIRECT GPIO
143 H17 RMII1_CRS_DV BIDIRECT RMII Carrier Sense / Data Valid
144 H18 RMII1_REFCLK BIDIRECT RMII Reference Clock
145
J1 DDR_D8 BIDIRECT DDR SDRAM DATA INPUT/OUTPUT
146 J2 DDR_DQM1 O DDR WRITE ENABLE / DATA MASK FOR DATA[15:8]
147 J3 DDR_VTP I VTP Compensation Resistor
148 J4 DDR_VREF I Voltage Reference Input
149 J5 VDDS_DDR VCC VDDS for DDR
150 J6 VSS GND GND
151 J7 VSS GND GND
152 J8 VSS GND GND
153 J9 VSS GND GND
154 J10 VSS GND GND
155 J11 VSS GND GND
156 J12 VDD_CORE VCC VDD for Core
157 J13 VDD_MPU VCC VDD for MPU
158 J14 VDDSHV4 VCC VDD for I/O
159 J15 RMII1_RXER BIDIRECT RMII Receive Data Error
160 J16 RMII1_TXEN BIDIRECT RMII Transmit Enable
161 J17 GPIO3[4] BIDIRECT GPIO
162 J18 UART4_RXD BIDIRECT UART Receive Data
AM3352BZCZ60 (YF449B00) MICROPROCESSOR (MPU)