Yaesu FT-902DM, Инструкция по эксплуатации

Страница: 34 / 55

A
portion of the
Q , 2 0 9
output is rectified by
0 1 2 1 9
an d
D , 2 2 0
(both 1 N60) ; this rectified
DC
voltage is amp lified by· DC amplifier
Q , 2 1 2
( 2SC
1 8 1 5Y ) to generate AGC voltage which controls
the gain of
Q , 2 0 9 ,
thus ob taining u nity signal
ou tpu t when the band is changed.
PLL UNIT ( PB-1 709A)
The sample signal from the VCO UNIT is fed to
the PLL mixer
Q 1 1 0 2
( TA7 3 1 0P ) , where the
sample signal is mixed with the heterodyne signal
( a t 5 . 0
-
5 . 5
MHz) delivered from the XTAL
UNIT through buffer amplifier
Q
1 1 0 1
( 2SC
1 8 1 S Y ) . The 5 . 0
-
5 . 5 MHz signal is fed through
amp lifier
Q 1 1 0 3
( 2SC 1 8 1 5 Y ) to
Q 1 1 0 6 ( SN
7 5450B ) , where the signal waveform is shaped
prior to being supplied to a phase detector
Q , 1 0 7
( MC4044P) ; here the phase of the signal is com­
pared with the p hase of the signal d elivered
through wave shaper
Q 1 1 0 6 ,
b uffer
Q 1 1 0 5
( 2SC
1 8 1 5Y ) , and amp lifier Q 1 1 0 4 ( 2 S K 1 9GR) from the
VFO UNIT.
Q 1 1 0 7
compares the phase of the two signals and
converts the phase difference into the VCV voltage
which controls the VCO frequency .
Q 1 1 0 8
( 2SC
1 8 1 5GR ) acts as an active low pass filter to rem ove
ripples from the VCV voltage.
When the VCO is unlocked ,
Q 1 1 0 9
( 2SC 1 8 1 5Y )
delivers the signal t o prevent receive o r transmit
action of the transceiver.
Q 1 1 1 0
( 7 8L08 ) and
Q 1 1 1 1
( 7 8 L05 ) are voltage
regulators.
Rio
100
/?,._ 7 RJo
0 0 1 � 0 1 2
· -
1 11
/, m o I��
IOO
2 S C 3 8 0 Y
I
L_
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
�J�t,,_J:J� IT
_ _
- 32--