Xycom XVME-560, Руководство пользователя

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XVME-560 Manual
September, 1984
3.4.1 Control Register Bit Definitions
(Write base+8lH)
D7
D6,D5:
D4:
D3
l
l
D2
l
Dl,D0:
A logic 1 written to D7 will force a conversion.
These two bits provide the “mode code** specifying the desired
operating mode as shown in Table 3-1 below.
Table 3-l. Mode Bits
Mode Bits
Mode 1 Mode 0
0 0
0
1
1 0
1 1
A/D Conversion Mode
Single Channel
Sequential Channel
Random Channel
External Trigger
These conversion modes are described in
detail in Section 3.5.
This bit is a software module reset. If this is set to a logic "1" and
then to a
logic
"0", the module will
be
reset except for
the
Control/Status register. The A/D converter is not reset, so a
minimum of 25
usec.
must
pass before
a
conversion
can be started.
This bit enables interrupts when set to a logic " 1 " .
Not used.
These bits control
the red
(SYSFAIL) and green (PASS) LEDs. The
red and green
LEDs provide
visual indication of
a module status.
0
A logic
" 0 "
turns on
the Red LED
(D0)
0
A logic “1” turns on
the Green LED (Dl)
The LEDs
will indicate the following
status (Table 3-2)
as
set forth
by the XYCOM architecture (described in Appendix
A).
Table 3-2.
LED
Status
Red Green
OFF O F F
OFF O N
ON O F F
ON O N
Module
Not operational
Passed diagnostics
Power-up/failed diagnostics
Undergoing diagnostics
NOTE
The AIN is a non-intelligent module so all diagnostics must be
performed by the system host.
3-4