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XVME-113 RAM/ROM Memory Module

October 1992

A-5

Table A-1. VMEbus Signal Identification (Continued)

Signal

Mnemonic

Connector

and

Pin Number

Signal Name and Description

SYSFAIL*

SYSRESET*

WRITE*

+5V STDBY

+5V

+12V

-12V

1C:10

1C:12

1A:14

1B:31

1A:32
1B:32
1C:32
2B:1,13,32

1C:31

1A:31

SYSTEM FAIL: Open-collector driven signal that indicates that a failure
has occurred in the system. It may be generated by any module on the
VMEbus.

SYSTEM RESET: Open-collector driven signal which, when low, will
cause the system to be reset.

WRITE: Three-state driven signal that specifies the data transfer cycle in
progress to be either read or written. A high level indicates a read operation,
a low level indicates a write operation.

+5 VDC STANDBY: This line su5 VDC to devices requiring
battery backup.

+5 VDC POWER: Used by system logic circuits.

+12 VDC POWER: Used by system logic circuits.

-12 VDC POWER: Used by system logic circuits.

Содержание XVME-113

Страница 1: ...XVME 113 RAM ROM Memory Module P N 74113 001 F 1998 XYCOM INC Printed in the United States of America retired...

Страница 2: ...enclosure must be fully shielded An example of such an enclosure is a Schroff 7U EMC RFI VME System chassis that includes a front cover to complete the enclosure The connection of nonshielded equipmen...

Страница 3: ...2 11 2 5 2 Address Modifier Decode 2 11 2 5 3 Memory Device Speed 2 13 2 5 4 Memory Device Type 2 14 2 5 5 Memory Device Size 2 17 2 5 6 Memory Backup Power 2 18 2 5 7 SYSRESET Driver 2 19 2 5 8 SYSF...

Страница 4: ...outs 2 12 2 7 Notched End of the Memory Chip 2 14 TABLE TITLE PAGE 1 1 XVME 113 Memory Module Hardware Specifications 1 4 1 2 Memory Module Environmental Specifications 1 5 2 1 Switch and Jumper List...

Страница 5: ...two contains 8 memory sites Each bank is designed to employ memory devices of the same type and speed and each bank can be independently configured via jumpers and switches in terms of VME Address Add...

Страница 6: ...module including functional and environmental specifications and VMEbus compliance information Chapter Two Information covering switch jumper options memory chip and cardcage installation procedures r...

Страница 7: ...113 RAM ROM Memory Module October 1992 2 3 1 3 MODULE OPERATIONAL DESCRIPTION Figure 1 1 below shows an operational block diagram of the XVME 113 RAM ROM Memory Module Figure 1 1 Operational Block Dia...

Страница 8: ...up to 1024K by 8 FLASH 128K by 8 up to 512K by 8 EEPROM 128K by 8 up to 512K by 8 Device Speeds Supported 50 100 150 200 ns Power Requirements 5 V 7A typ 9 A max Battery Rating 1 9 Amp hours Battery L...

Страница 9: ...o 185 F Humidity 5 to 95 RH non condensing Extreme low humidity conditions may require special protection against static discharge Altitude Operating Sea level to 10 000 ft 3048 m Non Operating Sea le...

Страница 10: ...Chapter 1 Introduction 1 6...

Страница 11: ......

Страница 12: ...Chapter 2 Installation 2 2...

Страница 13: ...XVME 113 RAM ROM Memory Module October 1992 2 3 0 1 2...

Страница 14: ...Chapter 2 Installation 2 4 3 1 1 1 13 14 15 16 7 2 89 2 89 9 9 9 9 3 4 5 6 97 9 9 9 97 9 9 9 9 9 9 9 4 9 9...

Страница 15: ...XVME 113 RAM ROM Memory Module October 1992 2 5 4 A B B B B C 9 A B 2 D B 4 8 8 8 3 4 9 9 0 0 1 0 E E E...

Страница 16: ...Chapter 2 Installation 2 6 3 7 2 2 3 8 1 1...

Страница 17: ...XVME 113 RAM ROM Memory Module October 1992 2 7 8 9 4 8 9 3 9 C 4 9 C 3 9 2 3 42 4 5 612 4 6 2 4 7 02 4 E 3 4 5 6 9 B 3 5 3 E...

Страница 18: ...Chapter 2 Installation 2 8 4 9 2 3 6 42 4 5 612 4 6 2 4 7 02 4 E 3 4 5 6 9 B 3 4 5 6 9 B 3 5 3 E...

Страница 19: ...XVME 113 RAM ROM Memory Module October 1992 2 9 4 3 9 5 C 5 C 9 C C 9 9 9 9...

Страница 20: ...Chapter 2 Installation 2 10 3...

Страница 21: ...XVME 113 RAM ROM Memory Module October 1992 2 11 4 8 3 9 F F F F F F 3 3 F F 4 8 85 1 1 B G B 1 1 1 1 5 9 8 9 9 9 G...

Страница 22: ...Chapter 2 Installation 2 12 5 2 1 3 2 H E I H E 8 2 1 8 E B B 8 B 2 B 1 B 8 B 2 1 5 2 H E I 2 H E 8 2 1 8 E B B 8 B 2 B 1 B 8 B E 1...

Страница 23: ...XVME 113 RAM ROM Memory Module October 1992 2 13 4 9 5 4 4 6 6 B 2 0 6 1 4 4 E E 2 1 6 1 4 4 E E E B B JE B B JE 3...

Страница 24: ...Chapter 2 Installation 2 14 4 3 9 5 9 9 9 B 2 0 6 1 7 0 4 9 9 9 9 E E E 9E 9E 9E 9E E 9EE 9 9 9 9 4 81 B 8 9 9 9 9 81 E B EE9 4 5 4 5 4 9...

Страница 25: ...XVME 113 RAM ROM Memory Module October 1992 2 15 9 B 2 1 4 4 9 9 9 9 E E E 9E 9E 9E 9E E 9EE 9 9 9 9 9 4 81 B 8 B 9 9 9 9 9 81 9 E B EE9 4 5 6 4 9 4 B 6...

Страница 26: ...Chapter 2 Installation 2 16 4 6 4 5...

Страница 27: ...XVME 113 RAM ROM Memory Module October 1992 2 17 6 4 4 9 5 9 C C 9 9 9 B C 2 0 7 J B 45J B 4 J B 3J B E E 2 1 7 J B 45J B 4 J B 3J B E E E...

Страница 28: ...Chapter 2 Installation 2 18 4 5 9 B A 4 B9 5 2 9 9 5 4 B9 4 4 B9 E 9 7 E 7 9EE EE E EE 4 B9 0 5 9 4 B9 0 4...

Страница 29: ...XVME 113 RAM ROM Memory Module October 1992 2 19 0 A H 88 9 A 9 H 0 H 5 9 A 9 H H 6 3 H 88 3 A 9 9 H 39 2 H 3 9 9 H 9 2 H 8 9 3 9 4 6 5 E E 3 54 E 6 E 6...

Страница 30: ...Chapter 2 Installation 2 20 4 5 E E B E 6 E 6 E E E B E...

Страница 31: ...XVME 113 RAM ROM Memory Module October 1992 2 21 4 3 8 8 3 C 4 8 3 B E E 4 9 J 53 J 53J 6 9 5 6 8 5...

Страница 32: ...Chapter 2 Installation 2 22 9...

Страница 33: ...1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1...

Страница 34: ...1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1...

Страница 35: ...NG THE XVME 113 INTO A CARDCAGE To install a board in the cardcage perform the following steps 1 Make certain that the particular cardcage slot which you are going to use is clear and accessible 2 Cen...

Страница 36: ...rews at the top and bottom of the front panel NOTE It should not be necessary to use excess pressure of force to engage the connectors If the board does not properly connect with the backplane remove...

Страница 37: ...te description of each of the RTC registers as well as procedures for programming the various functions of the RTC The following is a list of Acronyms and Abbreviations used in this chapter ACRONYM AN...

Страница 38: ...le 3 2 shows data bit definitions Table 3 1 Register Addressing Offset from 1K Base Address Real Time Clock Configuration Register 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1...

Страница 39: ...Bank 1 upper bit Determines Memory Size Bank 1 lower bit 00 128K x 8 01 256K x 8 10 512K x 8 11 1024K x 8 Determines Memory Type Bank 2 upper bit Determines Memory Type Bank 2 lower bit 00 EPROM 01 S...

Страница 40: ...mo1 Month Counter 0Fh c y80 c y40 c y20 c y10 c y8 c y4 c y2 c y1 Year Counter 11h ENB 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz 64 Hz Alarm 13h ENB a s40 a s20 a s10 a s8 a s4 a s2 a s1 Seconds Alarm 15h...

Страница 41: ...he procedure for reading the RTC time in section 3 4 3 The 64 Hz Counter Register can only be reset using the RESET or 30 sec ADJ operations Refer to the description of these bits in Control Register...

Страница 42: ...which the RTC triggers an alarm condition Bit 7 of each of these registers is the register s enable ENB bit If an alarm register s ENB bit is set the RTC uses that register in its comparison to its co...

Страница 43: ...main set as long as the corresponding counter registers match the alarm registers When the alarm condition is no longer true the AF bit will automatically be cleared to 0 The AF bit may be reset by wr...

Страница 44: ...Seconds Counter Register value is less than 30 the Minutes Counter Register is unchanged Otherwise a carry will occur in the Minutes Counter Register The 64 Hz Counter Register and the Seconds Counter...

Страница 45: ...on As long as battery backup is enabled the RTC will not need to be initialized after the VMEbus system is powered up Follow the procedure for initializing the RTC registers as indicated in the flow...

Страница 46: ...ip 3 Since interrupts from the RTC are not used on the XVME 113 clear the CIE bit 4 of Control Register A and AIE bit 3 of Control Register A bits to 0 4 The Start Stop bit bit 0 of Control Register B...

Страница 47: ...Register B Follow the procedure below to set the RTC time with the clock stopped 1 Stop the RTC by clearing the Start Stop bit bit 0 of Control Register B to 0 The clock will then be stopped but no re...

Страница 48: ...1 NO Repeat for each register to be set Follow the procedure below to set the RTC time with the clock running 1 Clear the CF bit in Control Register A to 0 Note To prevent the AF bit from being cleare...

Страница 49: ...to be concerned with handling an interrupt from a carry operation The CIE and AIE bits in Control Register A should always be written with 0 2 Clear the CF bit in Control Register A to 0 Note To preve...

Страница 50: ...ol Register A Monitor the alarm time Check AF Follow the procedure below to setup and monitor the alarm function 1 Since interrupts are not used there is no need to be concerned with handling an inter...

Страница 51: ...g term timer and will keep accurate track of the year month and day If used in this application setting the correct date is required The RTC will properly handle the number of days in each of the twel...

Страница 52: ......

Страница 53: ...ded or that the required input voltage levels are not being met INTERRUPT ACKNOWLEDGE IN Totem pole driven signal IACKIN and IACKOUT signals form a daisy chained acknowledge The IACKIN signal indicate...

Страница 54: ...ated by the current DTB master to indicate that it is using the bus BUS CLEAR Totem pole driven signal generated by the bus arbitrator to request release by the DTB master if a higher level is request...

Страница 55: ...hree state driven signal that indicates during byte and word transfers that a data transfer will occur on data bus lines D00 D07 DATA STROBE 1 Three state driven signal that indicates during byte and...

Страница 56: ...e daisy chain INTERRUPT REQUEST 1 7 Open collector driven signals generated by an interrupter which carry prioritized interrupt requests Level seven is the highest priority LONGWORD Three state driven...

Страница 57: ...rred in the system It may be generated by any module on the VMEbus SYSTEM RESET Open collector driven signal which when low will cause the system to be reset WRITE Three state driven signal that speci...

Страница 58: ...7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D00 D01 D02 D03 D04 D05 D06 D07 GND SYSCLK GND DS1 DS0 WRITE GND DTACK GND AS GND IACK IACKIN IACKOUT AM4 A07 A06 A05 A04 A0...

Страница 59: ...B 1 2 9 9 9 9 9 0 A B 7A 3 9 2 9 9 B 9 H H 2 H HB G H B HB G H H 4 5 9 87 9 9 8 9 H4 2 H 2 H 4 2 H 2 6 9 87 9 9 8 9 H H H 9 C 87 9 9 C 8 9 H J H 45J H4 J H 3J 9 3 97 8 H 97H9 4 5 H 9 H...

Страница 60: ...ix B Quick Reference Guide B 2 9 9 1 A B 7A 3 9 2 9 9 B 9 H H 2 H HB G H B HB G H H 4 5 9 87 9 9 8 9 H4 2 H 2 H 4 2 H 2 6 9 87 9 9 8 9 H H H 9 C 87 9 9 C 8 9 H J H 45J H4 J H 3J 4 9 3 97 8 H 97H9 6 9...

Страница 61: ...M Memory Module October 1992 B 3 9 9 B 4 B 3 B C B C B B B C B C B6 B 9 B 9 8 B 9 8 B C 9 8 B C 9 8 B 9 8 B 9 8 B C 9 8 B C 9 8 J 5 7 8 6 9 3 9 3 6 3 3 4 5 6 4 3 B 2 HB H HB H HB H HB H HB H HB H HB H...

Страница 62: ...9 4 9 4 5 9 2 9 5 4 4 4 E 9 7 7 9EE EE E 9 5 B 9 5 4 2 2 4 2 2 1 K 4 4 K 4 4 4 4 4 4 4 4 1 K 54 4 4 4 54 4 4 4 1 L 1 K 45 45 45 45 4 K 4 4 5 K 4 4 4 4 9 K 66 4 6 4 66 4 6 4 9 K 3 4 4 3 4 4 4 92 K 45 5...

Страница 63: ...ion among CS1 going high and WE going high Twp is measured from the beginning of write to the end of write 2 Tas is measured from the address valid at the beginning of write 3 Twr is measured from the...

Страница 64: ...Appendix B Quick Reference Guide B 6 Figure B 2 Read Timing Waveform...

Страница 65: ...C 1 APPENCIX C BLOCK DIAGRAM ASSEMBLY DRAWING SCHEMATICS Figure C 1 XVME 113 Block Diagram...

Страница 66: ...Appendix C Block Diagram Assembly Drawing Schematics C 2 Figure C 2 Assembly Drawing...

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