Chapter 3 – Real Time Clock
3-4
Table 3-3. RTC Register Map
RTC
Reg.
Offset
Bit Definitions
Register Name
01h
*
1 Hz
2 Hz
4 Hz
8 Hz
16 Hz
32 Hz
64 Hz
64 Hz Counter
03h
*
c-s
40
c-s
20
c-s
10
c-s
8
c-s
4
c-s
2
c-s
1
Seconds Counter
05h
*
c-mi
40
c-mi
20
c-mi
10
c-mi
8
c-mi
4
c-mi
2
c-mi
1
Minutes Counter
07h
*
*
c-h
20
c-h
10
c-h
8
c-h
4
c-h
2
c-h
1
Hours Counter
09h
*
*
*
*
*
c-w
4
c-w
2
c-w
1
Day of Week Counter
0Bh
*
*
c-d
20
c-d
10
c-d
8
c-d
4
c-d
2
c-d
1
Day Counter
0Dh
*
*
*
c-mo
10
c-mo
8
c-mo
4
c-mo
2
c-mo
1
Month Counter
0Fh
c-y
80
c-y
40
c-y
20
c-y
10
c-y
8
c-y
4
c-y
2
c-y
1
Year Counter
11h
ENB
1 Hz
2 Hz
4 Hz
8 Hz
16 Hz
32 Hz
64 Hz
64 Hz Alarm
13h
ENB
a-s
40
a-s
20
a-s
10
a-s
8
a-s
4
a-s
2
a-s
1
Seconds Alarm
15h
ENB
a-mi
40
a-mi
20
a-mi
10
a-mi
8
a-mi
4
a-mi
2
a-mi
1
Minutes Alarm
17h
ENB
*
a-h
20
a-h
10
a-h
8
a-h
4
a-h
2
a-h
1
Hours Alarm
19h
ENB
*
*
*
*
a-w
4
a-w
2
a-w
1
Day of Week Alarm
1Bh
ENB
*
a-d
20
a-d
10
a-d
8
a-d
4
a-d
2
a-d
1
Day Alarm
1Dh
CF
*
*
CIE
AIE
*
*
AF
Control
Register A
1Fh
RAM
7
RAM
6
RAM
5
RAM
4
TEST
30 sec
ADJ
RESET
Start/
Stop
Control
Register B
NOTE
Bits indicated by '*' are unused. These bits are unchanged during write operations and
will always read '0' during read operations.
Содержание XVME-113
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Страница 15: ...XVME 113 RAM ROM Memory Module October 1992 2 5 4 A B B B B C 9 A B 2 D B 4 8 8 8 3 4 9 9 0 0 1 0 E E E...
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Страница 19: ...XVME 113 RAM ROM Memory Module October 1992 2 9 4 3 9 5 C 5 C 9 C C 9 9 9 9...
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Страница 64: ...Appendix B Quick Reference Guide B 6 Figure B 2 Read Timing Waveform...
Страница 65: ...C 1 APPENCIX C BLOCK DIAGRAM ASSEMBLY DRAWING SCHEMATICS Figure C 1 XVME 113 Block Diagram...
Страница 66: ...Appendix C Block Diagram Assembly Drawing Schematics C 2 Figure C 2 Assembly Drawing...
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