3115T Thin Line Industrial Flat Panel PC Chapter 3 – POS-370 Control Board and BIOS Setup
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141876(E)
Setting
Description
SDWCLK Control CS#/CKE
This item controls the phase of SDWCLK used for chip set select
signals pin that lags ahead SDCLK.
The choice: Enabled, Disabled.
SDWCLK Control MA/SRAS
This item controls the phase of SDWCLK used for MA/ SRAS signals
that lags ahead SDCLK.
The choice: +5.0ns~-2.5ns (Default 0.0ns)
SDWCLK Control DQM/MD
This item controls the phase of SDWCLK used for DQM/MD signals that
lags ahead SDCLK. The choice: +5.0ns~-2.5ns (Default 0.0ns)
EGMRCLK Control
This item controls the phase of EGMRCLK that lags behind SDCLK.
The choice: -1.0ns~+6.5ns (Default 0.0ns)
EGMWCLK Control
This item controls the phase of EGMWCLK that lags ahead SDCLK.
The choice: +5.0ns~-2.5ns (Default 0.0ns)
System BIOS Cacheable
Selecting ‘Enabled’ allows caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance. However, if any program writes to this
memory area, a system error may result.
The choice: Enabled, Disabled.
Video RAM Cacheable
Selecting ‘Enabled’ allows caching of the video RAM, resulting in better system
performance. However, if any program writes to this memory area, a system error
may result.
The choice: Enabled, Disabled.
Memory Hole at 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use
this area of system memory usually discusses their memory requirements.
The choice: Enabled, Disabled.
AGP Aperture Size
This item allows you to select the size of Accelerated Graphics Port (AGP) aperture.
The aperture is a portion of the PCI memory address range dedicated for graphics
memory address space. Host cycles that hit the aperture range are forwarded to the
AGP without any translation.
The choice: 4M, 8M, 16M, 32M, 64M, 128M, 256M.