3115T Thin Line Industrial Flat Panel PC Chapter 3 – POS-370 Control Board and BIOS Setup
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141876(E)
Table 3–20. Advanced DRAM Control ½ Settings
Setting
Description
Auto Configuration
This item will automatically configure the chipset timing. Select ‘Manual’
to enter a specific timing value.
The choice: Manual, Auto, 100MHZ, 133MHZ.
SDRAM RAS Active Time
This item defines SDRAM ACT to PRE command period.
The choice: 6T, 7T, 5T, 4T.
SDRAM RAS Pre-charge Time
This item defines SDRAM PRE to ACT command period.
The choice: 3T, 2T, 4T, Reserved.
RAS to CAS Delay
This item defines SDRAM ACT to Read/Write command period.
The choice: 3T, 2T, 4T, Reserved.
DRAM Background Command
This item is lead-off time control for DRAM background command.
When 'Delay 1T' is selected, background commands are issued one
clock after the memory address (MA) command has been issued. When
'Normal' is selected, background commands and MA are issued at the
same time.
The choice: Delay 1T, Normal.
LD-Off DRAM RD/WR Cycles
The item is lead-off time control for DRAM Read/Write Cycles. When
'Delay 1T' is selected, the memory read/write command is issued one
clock pulse after the memory address (MA) is issued. When 'Normal' is
selected, the read/write command and MA are issued at the same time.
The choice: Delay 1T, Normal.
Write Recovery Time
This item defines the Data-in to PRE command period.
The choice: 1T, 2T
VCM REF To ACT/REF Delay
This item defines VCM REF to REF/ACT command period. The
choice: 10T, 9T.
VCM ACCT To ACT/REF Delay This item defines VCM ACT to ACT/REF command period.
The choice: 10T, 9T, 8T, Reserved.
Early CKE Delay 1T Cntrl
When this item is enabled, CKE is driven out from flip-flop. It is used
when system operates under low frequency and CKE delay adjustment
method defined in the 'Early CKE Delay Adjust' setting, which cannot
meet the setup time and hold time requirements.
The choice: Normal, Delay 1T.
Early CKE Delay Adjust
This item controls the timing for CKE. Various delay options are
provided to ensure that CKE can meet the SDRAM setup time and hold
time specification when CKE is driven out.
The choice: 1ns, 2ns, 3ns, 4ns, 5ns, 6ns, 7ns, 8ns.
Mem Command Output Time
This item is to control the timing to drive memory command onto
memory bus.
The choice: Normal, Delay 1T.
SDRAM/VCM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing.
The choice: 2, 3, SPD
SDRCLK Control
This item controls the phase of SDRCLK that lags behind SDCLK.
The choice: Enabled, Disabled.
