VC7203 GTX Transceiver Characterization Board
51
UG957 (v1.0) October 10, 2012
VC7203 Board UCF Listing
NET IO_L22P_T3_17 LOC = AJ40 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L22N_T3_17 LOC = AJ41 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L23P_T3_17 LOC = AK39 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L23N_T3_17 LOC = AL39 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L24P_T3_17 LOC = AJ42 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_L24N_T3_17 LOC = AK42 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_25_VRP_17 LOC = AG37 | IOSTANDARD=LVCMOS18; # Bank 17
NET IO_0_VRN_18 LOC = N35 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L1P_T0_AD0P_18 LOC = T34 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L1N_T0_AD0N_18 LOC = R35 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L2P_T0_AD8P_18 LOC = N33 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L2N_T0_AD8N_18 LOC = N34 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L3P_T0_DQS_AD1P_18 LOC = R33 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L3N_T0_DQS_AD1N_18 LOC = R34 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L4P_T0_18 LOC = P35 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L4N_T0_18 LOC = P36 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L5P_T0_AD9P_18 LOC = T32 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L5N_T0_AD9N_18 LOC = R32 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L6P_T0_18 LOC = P32 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L6N_T0_VREF_18 LOC = P33 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L7P_T1_AD2P_18 LOC = T36 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L7N_T1_AD2N_18 LOC = R37 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L8P_T1_AD10P_18 LOC = P37 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L8N_T1_AD10N_18 LOC = P38 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L9P_T1_DQS_AD3P_18 LOC = U34 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L9N_T1_DQS_AD3N_18 LOC = T35 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L10P_T1_AD11P_18 LOC = R38 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L10N_T1_AD11N_18 LOC = R39 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L11P_T1_SRCC_18 LOC = U37 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L11N_T1_SRCC_18 LOC = U38 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L12P_T1_MRCC_18 LOC = U39 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L12N_T1_MRCC_18 LOC = T39 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L13P_T2_MRCC_18 LOC = U36 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L13N_T2_MRCC_18 LOC = T37 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L14P_T2_SRCC_18 LOC = V35 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L14N_T2_SRCC_18 LOC = V36 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L15P_T2_DQS_18 LOC = V33 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L15N_T2_DQS_ADV_B_18 LOC = V34 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L16P_T2_A28_18 LOC = W36 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L16N_T2_A27_18 LOC = W37 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L17P_T2_A26_18 LOC = U32 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L17N_T2_A25_18 LOC = U33 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L18P_T2_A24_18 LOC = W32 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L18N_T2_A23_18 LOC = W33 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L19P_T3_A22_18 LOC = V39 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L19N_T3_A21_VREF_18 LOC = V40 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L20P_T3_A20_18 LOC = T40 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L20N_T3_A19_18 LOC = T41 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L21P_T3_DQS_18 LOC = W41 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L21N_T3_DQS_A18_18 LOC = W42 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L22P_T3_A17_18 LOC = U41 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L22N_T3_A16_18 LOC = T42 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L23P_T3_FOE_B_18 LOC = W38 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L23N_T3_FWE_B_18 LOC = V38 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L24P_T3_RS1_18 LOC = V41 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_L24N_T3_RS0_18 LOC = U42 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_25_VRP_18 LOC = W35 | IOSTANDARD=LVCMOS18; # Bank 18
NET IO_0_VRN_19 LOC = L36 | IOSTANDARD=LVCMOS18; # Bank 19
NET DUT_PMB_ALERT LOC = E40 | IOSTANDARD=LVCMOS18; # Bank 19
NET DUT_PMB_CTRL LOC = D40 | IOSTANDARD=LVCMOS18; # Bank 19
NET DUT_PMB_CLK LOC = A40 | IOSTANDARD=LVCMOS18; # Bank 19
NET DUT_PMB_DATA LOC = A41 | IOSTANDARD=LVCMOS18; # Bank 19
NET IO_L3P_T0_DQS_19 LOC = D41 | IOSTANDARD=LVCMOS18; # Bank 19
NET IO_L3N_T0_DQS_19 LOC = D42 | IOSTANDARD=LVCMOS18; # Bank 19
NET IO_L4P_T0_19 LOC = B41 | IOSTANDARD=LVCMOS18; # Bank 19
NET IO_L4N_T0_19 LOC = B42 | IOSTANDARD=LVCMOS18; # Bank 19
NET IO_L5P_T0_19 LOC = F42 | IOSTANDARD=LVCMOS18; # Bank 19
NET USER_SW1 LOC = E42 | IOSTANDARD=LVCMOS18; # Bank 19
NET USER_SW2 LOC = C40 | IOSTANDARD=LVCMOS18; # Bank 19
NET USER_SW3 LOC = C41 | IOSTANDARD=LVCMOS18; # Bank 19
NET USER_SW4 LOC = H40 | IOSTANDARD=LVCMOS18; # Bank 19
NET USER_SW5 LOC = H41 | IOSTANDARD=LVCMOS18; # Bank 19
NET USER_SW6 LOC = H39 | IOSTANDARD=LVCMOS18; # Bank 19
NET USER_SW7 LOC = G39 | IOSTANDARD=LVCMOS18; # Bank 19
NET USER_SW8 LOC = G41 | IOSTANDARD=LVCMOS18; # Bank 19
NET IO_L9N_T1_DQS_19 LOC = G42 | IOSTANDARD=LVCMOS18; # Bank 19
NET IO_L10P_T1_19 LOC = F40 | IOSTANDARD=LVCMOS18; # Bank 19
NET IO_L10N_T1_19 LOC = F41 | IOSTANDARD=LVCMOS18; # Bank 19
NET IO_L11P_T1_SRCC_19 LOC = J40 | IOSTANDARD=LVCMOS18; # Bank 19
NET IO_L11N_T1_SRCC_19 LOC = J41 | IOSTANDARD=LVCMOS18; # Bank 19
NET CLK_DIFF_2_P LOC = K39 | IOSTANDARD=LVCMOS18; # Bank 19
