Xilinx VC7203, Руководство пользователя

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VC7203 GTX Transceiver Characterization Board www.xilinx.com 21
UG957 (v1.0) October 10, 2012
Detailed Description
Figure 1-9 Shows the user test I/O connector J125 (Callout 26 , Figure 1-2 ).
User Push Buttons (Active High)
Callout 24 , Figure 1-2 .
SW4 and SW5 are active-High user push buttons that are connected to user I/O pins on the
FPGA as shown in
Table 1-12 . These switches can be used for any purpose determined by
the user.
GTX Transceivers and Reference Clocks
Callout 4 , Figure 1-2 .
The VC7203 board provides access to all GTX transceiver and reference clock pins on the
FPGA as shown in
Figure 1-10 . The GTX transceivers are grouped into nine sets of four
RX-TX lanes . Four lanes are referred to as a Quad .
Note:
QUAD 111 and QUAD 112 do not connect to pins on the XCV4 8 5T.
Table 1-11: User DIP Switches
U1 FPGA Pin Net Name
DIP Switch
Reference
Designator
J125 Test Header Pin
E42 USER_SW1
SW2
2
C40 USER_SW2 4
C41 USER_SW3 6
H40 USER_SW4 8
H41 USER_SW5 10
H39 USER_SW6 12
G39 USER_SW7
G41 USER_SW8
X-Ref Target - Figure 1-9
Figure 1-9: User Test I/O
UG9 3 2_C1_09_100712
U S ER_ S W1
9
8 7
6 5
4 3
2
10
1
12 11
J125
GND
U S ER_ S W2
U S ER_ S W 3
U S ER_ S W4
U S ER_ S W5
U S ER_ S W6
Table 1-12: User Push Buttons
U1 FPGA Pin Net Name
Reference
Designator
P41 USER_PB1 SW5
N41 USER_PB2 SW4