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VC7203 GTX Transceiver Characterization Board

UG957 (v1.0) October 10, 2012

Chapter 1:

VC7203 Board Features and Operation

User LEDs (Active High)

Callout

Figure 1-2

DS13 through DS20 are eight active-High LEDs that are connected to user I/O pins on the
FPGA as shown in

Table 1-11

These LEDs can be used to indicate status or any other

purpose determined by the user.

User DIP Switches (Active High) and I/O Header

Callout

Figure 1-2

The DIP switch SW2 provides a set of eight active-High switches that are connected to user
I/O pins on the FPGA as shown in

Table 1-11

. These pins can be used to set control pins or

any other purpose determined by the user. Six of the eight I/Os also map to 2 x 6 test
header J125 providing external access for these pins (callout

Figure 1-2

.).

J17

CM_CTRL_23

107

J20

CM_RST

Table 1-9:

SuperClock-2 FPGA I/O Mapping

(Cont’d)

U1 FPGA Pin

Net Name

J82 Pin

Table 1-10:

User LEDs

U1 FPGA Pin

Net Name

Reference

Designator

M37

APP_LED1

DS19

M38

APP_LED2

DS20

R42

APP_LED3

DS17

P42

APP_LED4

DS18

N38

APP_LED5

DS16

M39

APP_LED6

DS15

R40

APP_LED7

DS13

P40

APP_LED8

DS14

Содержание VC7203

Страница 1: ...VC7203 Virtex 7 FPGA GTX Transceiver Characterization Board User Guide UG957 v1 0 October 10 2012...

Страница 2: ...including your use of the Materials including for any direct indirect special incidental or consequential loss or damage including loss of data profits goodwill or any type of loss or damage suffered...

Страница 3: ...15 FPGA Configuration 15 PROG_B Push Button 17 DONE LED 17 INIT LED 17 System ACE SD Controller 17 System ACE SD Controller Reset 17 System ACE SD Configuration Address DIP Switches 17 200 MHz 2 5V LV...

Страница 4: ...tion Board UG957 v1 0 October 10 2012 Solution Centers 61 Further Resources 61 References 62 Appendix E Regulatory and Compliance Information Declaration of Conformity 63 Directives 63 Standards 63 El...

Страница 5: ...However certain interfaces that are available in larger density devices may not be available in the XC7V485T device for example GTX QUAD_111 GTX QUAD_112 FMC 3 etc Unsupported interfaces are highlight...

Страница 6: ...1 1 Figure 1 1 VC7203 Board Block Diagram UG957_c1_01_090512 FPGA Power Source On board Regulation Board Utility Power On board Regulation Push Buttons DIP Switches and LEDs SuperClock 2 Module Inter...

Страница 7: ...7 XC7V485T 3 FFG1761E FPGA page 15 2 SW1 Power switch page 9 3 J2 12V Mini Fit connector page 8 4 J84 J85 J86 J158 J159 J160 J161 J162 J89 GTX transceiver connector pads Q111 Q112 Q113 Q114 Q115 Q116...

Страница 8: ...DS5 DS6 DS8 DS9 DS10 DS26 DS27 DS28 DS29 Status LEDS for FPGA logic transceiver and utility power 17 J199 J200 J201 J202 J203 J204 Power regulation jumpers for onboard regulators 18 J28 J29 J31 J32 J...

Страница 9: ...provide no reverse polarity protection use a power supply with a current limit set at 6A max Caution Do NOT apply 12V power to more than a single input source For example do not apply power to J2 and...

Страница 10: ..._c1_03_100712 MGTVCCAUX MGTAVTT MGTAVCC VCCAUX VCCINT VCCAUX_IO VCCBRAM VCCO_HR VCCO_HP Power Supply 12V PWR IN J2 or J29 or J131 Power Controller 1 UCD9248PFC U9 Switching Regulators 2 Phases 1 0V at...

Страница 11: ...r 10A 0 6V to 3 6V VCCO_HR 1 8V default Utility PTH12060W U2 Fixed switching regulator 10A UTIL_5V0 5 0V PTH12020W U13 Fixed switching regulator 18A UTIL_3V3 3 3V PTH12020W U52 Fixed switching regulat...

Страница 12: ...ddress 54 are wired to the same PMBus The PMBus connector J26 callout 20 Figure 1 2 is provided for use with the TI USB Interface Adapter PMBus pod and associated TI GUI References More information ab...

Страница 13: ...e MUST be removed when providing external power to the GTX transceiver rails Information about the four 7 Series GTX power supply modules included with the KC724 kit is available from the vendor websi...

Страница 14: ...nnections are detailed in Table 1 5 Figure 1 6 shows the heatsink fan power connector J121 X Ref Target Figure 1 5 Figure 1 5 Active FPGA Heatsink Table 1 5 Fan Power Connections Fan Wire Header Pin B...

Страница 15: ...gure 1 2 System ACE SD callout 7 Figure 1 2 JTAG cable connector callout 6 Figure 1 2 The VC7203 board comes with an embedded USB to JTAG configuration module U8 which allows a host computer to access...

Страница 16: ...e chain J1 jumper OFF Installing the J1 jumper adds the FMC interfaces as well X Ref Target Figure 1 7 Figure 1 7 JTAG Chain UG957_c1_07_100712 FMC1_PRSNT_M2C_L FMC2_PRSNT_M2C_L FMC1 HPC Connector TDI...

Страница 17: ...the FPGA The SD card connects to the SD card connector J211 callout 7 Figure 1 2 located directly below the System ACE SD controller on the back side of the board System ACE SD Controller Reset Press...

Страница 18: ...in Table 1 8 SuperClock 2 Module Callout 10 Figure 1 2 The SuperClock 2 module connects to the clock module interface connector J82 and provides a programmable low noise and low jitter clock source f...

Страница 19: ...M_LVDS1_N 3 L12 CM_LVDS2_P 9 L11 CM_LVDS2_N 11 BA12 CM_LVDS3_P 17 BB12 CM_LVDS3_N 19 K19 CM_GCLK_P 25 J18 CM_GCLK_N 27 C19 CM_CTRL_0 61 B19 CM_CTRL_1 63 A16 CM_CTRL_2 65 A15 CM_CTRL_3 67 A20 CM_CTRL_4...

Страница 20: ...DIP switch SW2 provides a set of eight active High switches that are connected to user I O pins on the FPGA as shown in Table 1 11 These pins can be used to set control pins or any other purpose deter...

Страница 21: ...sceiver and reference clock pins on the FPGA as shown in Figure 1 10 The GTX transceivers are grouped into nine sets of four RX TX lanes Four lanes are referred to as a Quad Note QUAD 111 and QUAD 112...

Страница 22: ...nce clocks CLK0 and CLK1 are brought out to a connector pad which interfaces with Samtec BullsEye connectors used with the Samtec HDR 155805 01 BEYE cable assembly Contact Samtec Inc for information a...

Страница 23: ...2 806 AA4 115_RX0_P 115 J83 2 898 AA3 115_RX0_N 115 J83 2 898 V2 115_TX1_P 115 J83 2 525 V1 115_TX1_N 115 J83 2 523 Y6 115_RX1_P 115 J83 2 489 Y5 115_RX1_N 115 J83 2 489 U4 115_TX2_P 115 J83 2 549 U3...

Страница 24: ...116 J84 2 555 M6 116_RX3_P 116 J84 2 821 M5 116_RX3_N 116 J84 2 821 K2 117_TX0_P 117 J85 2 617 K1 117_TX0_N 117 J85 2 616 K6 117_RX0_P 117 J85 2 886 K5 117_RX0_N 117 J85 2 886 J4 117_TX1_P 117 J85 2 4...

Страница 25: ...86 2 680 A4 118_TX3_P 118 J86 3 044 A3 118_TX3_N 118 J86 3 044 A8 118_RX3_P 118 J86 3 515 A7 118_RX3_N 118 J86 3 515 Table 1 14 GTX Transceiver Reference Clock Inputs U1 FPGA Pin Net Name Quad Connect...

Страница 26: ...e FPGA and the CP2103 are listed in Table 1 16 The bridge device also provides as many as 4 GPIO signals that can be defined by the user for status and control information Table 1 17 E8 118_REFCLK1_P...

Страница 27: ...nector is a 10 x 40 position socket See Appendix B VITA 57 1 FMC Connector Pinouts for a cross reference of signal names to pin coordinates FMC1 HPC connector JA2 provides connectivity for 69 differen...

Страница 28: ...P H4 AK32 FMC1_CLK0_M2C_N H5 AL31 FMC1_CLK1_M2C_P G2 AL32 FMC1_CLK1_M2C_N G3 AD32 FMC1_CLK2_BIDIR_P K4 AD33 FMC1_CLK2_BIDIR_N K5 AC34 FMC1_CLK3_BIDIR_P J2 AD35 FMC1_CLK3_BIDIR_N J3 AV40 FMC1_HA00_CC_P...

Страница 29: ...C1_HA16_N E16 AB33 FMC1_HB00_CC_P K25 AC33 FMC1_HB00_CC_N K26 AF35 FMC1_HB01_P J24 AF36 FMC1_HB01_N J25 AE37 FMC1_HB02_P F22 AF37 FMC1_HB02_N F23 AF34 FMC1_HB03_P E21 AG34 FMC1_HB03_N E22 AD36 FMC1_HB...

Страница 30: ...15_N J34 Y32 FMC1_HB16_P F34 Y33 FMC1_HB16_N F35 AU38 FMC1_LA00_CC_P G6 AV38 FMC1_LA00_CC_N G7 AU39 FMC1_LA01_CC_P D8 AV39 FMC1_LA01_CC_N D9 AN38 FMC1_LA02_P H7 AP38 FMC1_LA02_N H8 AM41 FMC1_LA03_P G9...

Страница 31: ...1_LA15_N H20 BA39 FMC1_LA16_P G18 BA40 FMC1_LA16_N G19 AK34 FMC1_LA17_CC_P D20 AL34 FMC1_LA17_CC_N D21 AJ33 FMC1_LA18_CC_P C22 AK33 FMC1_LA18_CC_N C23 AM36 FMC1_LA19_P H22 AN36 FMC1_LA19_N H23 AJ36 FM...

Страница 32: ...L29 FMC1_LA32_P H37 AL30 FMC1_LA32_N H38 AH29 FMC1_LA33_P G36 AH30 FMC1_LA33_N G37 AM38 FMC1_PRSNT_M2C_L H2 Table 1 19 VITA 57 1 FMC1 HPC Connections at JA3 U1 FPGA Pin Net Name FMC Pin E34 FMC2_CLK0_...

Страница 33: ...FMC2_HA08_P F10 E39 FMC2_HA08_N F11 J37 FMC2_HA09_P E9 J38 FMC2_HA09_N E10 H38 FMC2_HA10_P K13 G38 FMC2_HA10_N K14 J36 FMC2_HA11_P J12 H36 FMC2_HA11_N J13 P25 FMC2_HA12_P F13 P26 FMC2_HA12_N F14 P22...

Страница 34: ...FMC2_HB07_P J27 G23 FMC2_HB07_N J28 G28 FMC2_HB08_P F28 G29 FMC2_HB08_N F29 K28 FMC2_HB09_P E27 J28 FMC2_HB09_N E28 H28 FMC2_HB10_P K31 H29 FMC2_HB10_N K32 K27 FMC2_HB11_P J30 J27 FMC2_HB11_N J31 M22...

Страница 35: ...H34 FMC2_LA07_P H13 H35 FMC2_LA07_N H14 K29 FMC2_LA08_P G12 K30 FMC2_LA08_N G13 J30 FMC2_LA09_P D14 H30 FMC2_LA09_N D15 L29 FMC2_LA10_P C14 L30 FMC2_LA10_N C15 J31 FMC2_LA11_P H16 H31 FMC2_LA11_N H17...

Страница 36: ...FMC2_LA23_P D23 C39 FMC2_LA23_N D24 B37 FMC2_LA24_P H28 B38 FMC2_LA24_N H29 E32 FMC2_LA25_P G27 D32 FMC2_LA25_N G28 B32 FMC2_LA26_P D26 B33 FMC2_LA26_N D27 E33 FMC2_LA27_P C26 D33 FMC2_LA27_N C27 C33...

Страница 37: ...3_CLK3_BIDIR_P J2 H13 FMC3_CLK3_BIDIR_N J3 AU14 FMC3_HA00_CC_P F4 AU13 FMC3_HA00_CC_N F5 AV13 FMC3_HA01_CC_P E2 AW13 FMC3_HA01_CC_N E3 AW12 FMC3_HA02_P K7 AY12 FMC3_HA02_N K8 BA15 FMC3_HA03_P J6 BA14...

Страница 38: ...FMC3_HB01_P J24 E15 FMC3_HB01_N J25 E14 FMC3_HB02_P F22 E13 FMC3_HB02_N F23 H16 FMC3_HB03_P E21 G16 FMC3_HB03_N E22 G12 FMC3_HB04_P F25 F12 FMC3_HB04_N F26 K12 FMC3_HB05_P E24 J12 FMC3_HB05_N E25 F15...

Страница 39: ...K14 FMC3_LA03_P G9 AK13 FMC3_LA03_N G10 AK15 FMC3_LA04_P H10 AL14 FMC3_LA04_N H11 AJ13 FMC3_LA05_P D11 AJ12 FMC3_LA05_N D12 AL16 FMC3_LA06_P C10 AL15 FMC3_LA06_N C11 AK12 FMC3_LA07_P H13 AL12 FMC3_LA0...

Страница 40: ...FMC3_LA19_P H22 AM19 FMC3_LA19_N H23 AK17 FMC3_LA20_P G21 AL17 FMC3_LA20_N G22 AM18 FMC3_LA21_P H25 AM17 FMC3_LA21_N H26 AK19 FMC3_LA22_P G24 AK18 FMC3_LA22_N G25 AM16 FMC3_LA23_P D23 AN16 FMC3_LA23_...

Страница 41: ...rd provides two options for providing the reference voltage for the analog to digital converter Either option can be selected by placing a shunt in one of two positions on the 3 pin VREF SEL header J1...

Страница 42: ...ures and Operation FMC1 FMC2 FMC3 An I2C component can be accessed by selecting the appropriate channel through the control register of the MUX as shown in Table 1 21 Table 1 21 I2C Channel Assignment...

Страница 43: ...tion Jumper Comments J4 UTIL_3V3 Upper Left AFX 1 2 J184 UTIL_2V5 Upper Left AFX 1 2 J24 UTIL_5V0 Upper Left AFX 1 2 J78 VTT_HR SOURCE Upper Left GND 1 2 Red 20A jumper J210 PMBUS CTRL Upper Left GND...

Страница 44: ...44 www xilinx com VC7203 GTX Transceiver Characterization Board UG957 v1 0 October 10 2012 Appendix A Default Jumper Settings...

Страница 45: ...P2_C2M_N GND GND DP3_C2M_P DP3_C2M_N GND GND DP4_C2M_P DP4_C2M_N GND GND DP5_C2M_P DP5_C2M_N GND RES1 GND GND DP9_M2C_P DP9_M2C_N GND GND DP8_M2C_P DP8_M2C_N GND GND DP7_M2C_P DP7_M2C_N GND GND DP6_M2...

Страница 46: ...46 www xilinx com VC7203 GTX Transceiver Characterization Board UG957 v1 0 October 10 2012 Appendix B VITA 57 1 FMC Connector Pinouts...

Страница 47: ...ank 12 NET IO_L10P_T1_AD11P_12 LOC AW27 IOSTANDARD LVCMOS18 Bank 12 NET IO_L10N_T1_AD11N_12 LOC AW28 IOSTANDARD LVCMOS18 Bank 12 NET IO_L11P_T1_SRCC_12 LOC AU28 IOSTANDARD LVCMOS18 Bank 12 NET IO_L11N...

Страница 48: ...13 NET IO_L19P_T3_13 LOC AR30 IOSTANDARD LVCMOS18 Bank 13 NET IO_L19N_T3_VREF_13 LOC AT30 IOSTANDARD LVCMOS18 Bank 13 NET IO_L20P_T3_13 LOC AU31 IOSTANDARD LVCMOS18 Bank 13 NET IO_L20N_T3_13 LOC AV31...

Страница 49: ...LVCMOS18 Bank 15 NET FMC1_LA11_P LOC AR42 IOSTANDARD LVCMOS18 Bank 15 NET FMC1_LA11_N LOC AT42 IOSTANDARD LVCMOS18 Bank 15 NET FMC1_LA01_CC_P LOC AU39 IOSTANDARD LVCMOS18 Bank 15 NET FMC1_LA01_CC_N LO...

Страница 50: ...TANDARD LVCMOS18 Bank 17 NET IO_L1P_T0_17 LOC AB41 IOSTANDARD LVCMOS18 Bank 17 NET IO_L1N_T0_17 LOC AB42 IOSTANDARD LVCMOS18 Bank 17 NET IO_L2P_T0_17 LOC W40 IOSTANDARD LVCMOS18 Bank 17 NET IO_L2N_T0_...

Страница 51: ...k 18 NET IO_L15N_T2_DQS_ADV_B_18 LOC V34 IOSTANDARD LVCMOS18 Bank 18 NET IO_L16P_T2_A28_18 LOC W36 IOSTANDARD LVCMOS18 Bank 18 NET IO_L16N_T2_A27_18 LOC W37 IOSTANDARD LVCMOS18 Bank 18 NET IO_L17P_T2_...

Страница 52: ...S18 Bank 31 NET FMC3_LA07_N LOC AL12 IOSTANDARD LVCMOS18 Bank 31 NET FMC3_LA08_P LOC AM13 IOSTANDARD LVCMOS18 Bank 31 NET FMC3_LA08_N LOC AN13 IOSTANDARD LVCMOS18 Bank 31 NET FMC3_LA09_P LOC AM12 IOST...

Страница 53: ...Y20 IOSTANDARD LVCMOS18 Bank 32 NET FMC3_HA08_N LOC BA20 IOSTANDARD LVCMOS18 Bank 32 NET FMC3_HA09_P LOC BA16 IOSTANDARD LVCMOS18 Bank 32 NET FMC3_HA09_N LOC BB16 IOSTANDARD LVCMOS18 Bank 32 NET FMC3_...

Страница 54: ...FMC2_LA00_CC_P LOC L31 IOSTANDARD LVCMOS18 Bank 34 NET FMC2_LA00_CC_N LOC K32 IOSTANDARD LVCMOS18 Bank 34 NET FMC2_HA00_CC_P LOC N30 IOSTANDARD LVCMOS18 Bank 34 NET FMC2_HA00_CC_N LOC M31 IOSTANDARD...

Страница 55: ...TANDARD LVCMOS18 Bank 36 NET FMC2_HB03_P LOC H25 IOSTANDARD LVCMOS18 Bank 36 NET FMC2_HB03_N LOC H26 IOSTANDARD LVCMOS18 Bank 36 NET FMC2_HB04_P LOC G21 IOSTANDARD LVCMOS18 Bank 36 NET FMC2_HB04_N LOC...

Страница 56: ...TANDARD LVCMOS18 Bank 37 NET USB_RTS_0_B LOC C31 IOSTANDARD LVCMOS18 Bank 37 NET USB_CTS_I_B LOC B31 IOSTANDARD LVCMOS18 Bank 37 NET IO_L19P_T3_37 LOC E30 IOSTANDARD LVCMOS18 Bank 37 NET IO_L19N_T3_VR...

Страница 57: ...ANDARD LVCMOS18 Bank 39 NET FMC3_HB02_P LOC E14 IOSTANDARD LVCMOS18 Bank 39 NET FMC3_HB02_N LOC E13 IOSTANDARD LVCMOS18 Bank 39 NET FMC3_HB03_P LOC H16 IOSTANDARD LVCMOS18 Bank 39 NET FMC3_HB03_N LOC...

Страница 58: ...LOC AM4 Bank 113 NET 113_RX2_P LOC AL6 Bank 113 NET 113_TX2_N LOC AM3 Bank 113 NET 113_REFCLK0_P LOC AH8 Bank 113 NET 113_RX2_N LOC AL5 Bank 113 NET 113_REFCLK0_N LOC AH7 Bank 113 NET 113_REFCLK1_N L...

Страница 59: ...X2_P LOC L2 Bank 117 NET 117_RX2_P LOC L6 Bank 117 NET 117_TX2_N LOC L1 Bank 117 NET 117_REFCLK0_P LOC K8 Bank 117 NET 117_RX2_N LOC L5 Bank 117 NET 117_REFCLK0_N LOC K7 Bank 117 NET 117_REFCLK1_N LOC...

Страница 60: ...CLK0_N LOC A9 Bank 119 NET 119_REFCLK1_N LOC C9 Bank 119 NET 119_REFCLK1_P LOC C10 Bank 119 NET 119_TX1_P LOC D4 Bank 119 NET 119_RX1_P LOC C6 Bank 119 NET 119_TX1_N LOC D3 Bank 119 NET 119_RX1_N LOC...

Страница 61: ...ctual property at all stages of the design cycle Topics include design assistance advisories and troubleshooting tips http www xilinx com support solcenters htm Further Resources The most up to date i...

Страница 62: ...e the Xilinx website at http www xilinx com support documentation index htm References The following websites provide supplemental material useful with this guide 1 Information about the power system...

Страница 63: ...standards are maintained by the European Committee for Electrotechnical Standardization CENELEC IEC standards are maintained by the International Electrotechnical Commission IEC Electromagnetic Compat...

Страница 64: ...ronic equipment WEEE The affixed product label indicates that the user must not discard this electrical or electronic product in domestic household waste This product complies with Directive 2002 95 E...

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